From 9e32ff3491b3af115896798af3fd8c3606aac50f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:14 -0500
Subject: ARM: Implement the VFP version of vabs.

---
 src/arch/arm/isa/formats/fp.isa | 16 +++++++++++++++-
 src/arch/arm/isa/insts/fp.isa   | 24 ++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 080174318..29b1470e9 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -554,7 +554,21 @@ let {{
                                 (IntRegIndex)vd, (IntRegIndex)vm);
                     }
                 } else {
-                    return new WarnUnimplemented("vabs", machInst);
+                    uint32_t vd;
+                    uint32_t vm;
+                    if (bits(machInst, 8) == 0) {
+                        vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
+                        vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
+                        return new VabsS(machInst,
+                                (IntRegIndex)vd, (IntRegIndex)vm);
+                    } else {
+                        vd = (bits(machInst, 22) << 5) |
+                             (bits(machInst, 15, 12) << 1);
+                        vm = (bits(machInst, 5) << 5) |
+                             (bits(machInst, 3, 0) << 1);
+                        return new VabsD(machInst,
+                                (IntRegIndex)vd, (IntRegIndex)vm);
+                    }
                 }
               case 0x1:
                 if (opc3 == 1) {
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index bffdde235..56edb23f2 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -282,4 +282,28 @@ let {{
     header_output += RegRegOpDeclare.subst(vnegDIop);
     decoder_output += RegRegOpConstructor.subst(vnegDIop);
     exec_output += PredOpExecute.subst(vnegDIop);
+
+    vabsSCode = '''
+        FpDest = fabsf(FpOp1);
+    '''
+    vabsSIop = InstObjParams("vabss", "VabsS", "RegRegOp",
+                                     { "code": vabsSCode,
+                                       "predicate_test": predicateTest }, [])
+    header_output += RegRegOpDeclare.subst(vabsSIop);
+    decoder_output += RegRegOpConstructor.subst(vabsSIop);
+    exec_output += PredOpExecute.subst(vabsSIop);
+
+    vabsDCode = '''
+        IntDoubleUnion cOp1, cDest;
+        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
+        cDest.fp = fabs(cOp1.fp);
+        FpDestP0.uw = cDest.bits;
+        FpDestP1.uw = cDest.bits >> 32;
+    '''
+    vabsDIop = InstObjParams("vabsd", "VabsD", "RegRegOp",
+                                     { "code": vabsDCode,
+                                       "predicate_test": predicateTest }, [])
+    header_output += RegRegOpDeclare.subst(vabsDIop);
+    decoder_output += RegRegOpConstructor.subst(vabsDIop);
+    exec_output += PredOpExecute.subst(vabsDIop);
 }};
-- 
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