From a12dbc3074d505789aeeacd312e3a708d7a1f03c Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 18 Aug 2006 00:17:21 -0400 Subject: Update reference outputs --HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd --- src/python/m5/objects/BaseCPU.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 01458aeb4..81e09c94c 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -6,7 +6,7 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.PhysicalMemory(Parent.any, "memory") + mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") if build_env['FULL_SYSTEM']: -- cgit v1.2.3