From a83e74b37adc26afe4e69e59ed0092dafa63fc09 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 4 Jan 2013 18:09:35 -0600
Subject: ARM: Keep a copy of the fpscr len and stride fields in the decoder.
 Avoid reading them every instruction, and also eliminate the last use of the
 thread context in the decoders.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
---
 src/arch/arm/decoder.cc    |  5 ++---
 src/arch/arm/decoder.hh    | 12 +++++++++++-
 src/arch/arm/isa.cc        |  1 +
 src/arch/arm/remote_gdb.cc |  2 +-
 4 files changed, 15 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 4001f7597..b5a73d68b 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -113,9 +113,8 @@ Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     data = inst;
     offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
     emi.thumb = pc.thumb();
-    FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
-    emi.fpscrLen = fpscr.len;
-    emi.fpscrStride = fpscr.stride;
+    emi.fpscrLen = fpscrLen;
+    emi.fpscrStride = fpscrStride;
 
     outOfBytes = false;
     process();
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index a5f2c88a5..9099e3e2e 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -58,6 +58,9 @@ class Decoder
     bool foundIt;
     ITSTATE itBits;
 
+    int fpscrLen;
+    int fpscrStride;
+
   public:
     void reset()
     {
@@ -69,7 +72,8 @@ class Decoder
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0)
+    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
+        fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
@@ -121,6 +125,12 @@ class Decoder
         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
     }
 
+    void setContext(FPSCR fpscr)
+    {
+        fpscrLen = fpscr.len;
+        fpscrStride = fpscr.stride;
+    }
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b253574c7..0df50a85e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -381,6 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
+                tc->getDecodePtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 37a46b052..4078630d6 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -293,7 +293,7 @@ RemoteGDB::setregs()
     }
 
     //FPSCR
-    context->setMiscRegNoEffect(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
+    context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
 }
 
 void
-- 
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