From b5e0a8f19ad5fa3d320b890d416d41f65de8707e Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Thu, 27 Sep 2018 16:49:30 +0100 Subject: dev-arm: Added unimplemented GICv2 GICC_DIR This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-by: Anouk Van Laer Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg --- src/dev/arm/gic_v2.cc | 3 +++ src/dev/arm/gic_v2.hh | 1 + 2 files changed, 4 insertions(+) (limited to 'src') diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 293c72f1f..1e58718f9 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -622,6 +622,9 @@ GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data) case GICC_APR3: warn("GIC APRn write ignored because not implemented: %#x\n", daddr); break; + case GICC_DIR: + warn("GIC DIR write ignored because not implemented: %#x\n", daddr); + break; default: panic("Tried to write Gic cpu at offset %#x\n", daddr); break; diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 4afad89f6..49465ad56 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -110,6 +110,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters GICC_APR2 = 0xd8, // active priority register 2 GICC_APR3 = 0xdc, // active priority register 3 GICC_IIDR = 0xfc, // cpu interface id register + GICC_DIR = 0x1000, // deactive interrupt register }; static const int SGI_MAX = 16; // Number of Software Gen Interrupts -- cgit v1.2.3