From ba4c224c390916fb489aa7179655c71d7fca1e13 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 12 Oct 2006 13:33:21 -0400
Subject: Fix problems with unCacheable addresses in timing-coherence

src/base/traceflags.py:
src/mem/physical.cc:
    Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
    Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
    Set the size properly on unCacheable accesses

--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
---
 src/base/traceflags.py           | 1 +
 src/mem/cache/cache_impl.hh      | 5 +++++
 src/mem/cache/miss/miss_queue.cc | 2 +-
 src/mem/physical.cc              | 4 ++++
 4 files changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index f871ce35f..c05f9e5b0 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -122,6 +122,7 @@ baseFlags = [
     'MSHR',
     'Mbox',
     'MemDepUnit',
+    'MemoryAccess',
     'O3CPU',
     'OzoneCPU',
     'OzoneLSQ',
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a68418f24..150abbe52 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -389,6 +389,11 @@ template<class TagStore, class Buffering, class Coherence>
 void
 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 {
+    if (pkt->req->isUncacheable()) {
+        //Can't get a hit on an uncacheable address
+        //Revisit this for multi level coherence
+        return;
+    }
     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
     MSHR *mshr = missQueue->findMSHR(blk_addr);
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index c7b0e0890..c23b542f5 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
 MSHR*
 MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
 {
-    MSHR* mshr = mq.allocate(pkt, blkSize);
+    MSHR* mshr = mq.allocate(pkt, size);
     mshr->order = order++;
     if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
         // Mark this as a cache line fill
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 7303f278e..f5a0ade15 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -201,12 +201,16 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
         if (pkt->req->isLocked()) {
             trackLoadLocked(pkt->req);
         }
+        DPRINTF(MemoryAccess, "Performing Read of size %i on address 0x%x\n",
+                pkt->getSize(), pkt->getAddr());
         memcpy(pkt->getPtr<uint8_t>(),
                pmemAddr + pkt->getAddr() - params()->addrRange.start,
                pkt->getSize());
     }
     else if (pkt->isWrite()) {
         if (writeOK(pkt->req)) {
+            DPRINTF(MemoryAccess, "Performing Write of size %i on address 0x%x\n",
+                    pkt->getSize(), pkt->getAddr());
             memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
                    pkt->getPtr<uint8_t>(), pkt->getSize());
         }
-- 
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