From be62a142cf0513bfa69f4837565889dcb447fae0 Mon Sep 17 00:00:00 2001 From: Ani Udipi Date: Fri, 1 Nov 2013 11:56:17 -0400 Subject: mem: Schedule time for DRAM event taking tRAS into account This patch changes the time the controller is woken up to take the next scheduling decisions. tRAS is now handled in estimateLatency and doDRAMAccess and we do not need to worry about it at scheduling time. The earliest we need to wake up is to do a pre-charge, row access and column access before the bus becomes free for use. --- src/mem/simple_dram.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc index c537006a1..280ab640d 100644 --- a/src/mem/simple_dram.cc +++ b/src/mem/simple_dram.cc @@ -1135,12 +1135,11 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) // The absolute soonest you have to start thinking about the // next request is the longest access time that can occur before - // busBusyUntil. Assuming you need to meet tRAS, then precharge, - // open a new row, and access, it is ~4*tRCD. + // busBusyUntil. Assuming you need to precharge, + // open a new row, and access, it is tRP + tRCD + tCL - - Tick newTime = (busBusyUntil > 4 * tRCD) ? - std::max(busBusyUntil - 4 * tRCD, curTick()) : + Tick newTime = (busBusyUntil > tRP + tRCD + tCL ) ? + std::max(busBusyUntil - (tRP + tRCD + tCL) , curTick()) : curTick(); if (!nextReqEvent.scheduled() && !stopReads){ -- cgit v1.2.3