From c3bd8eb1214cbebbc92c7958b80aa06913bce3ba Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 27 Nov 2019 15:48:22 +0000 Subject: cpu: Fix coding style (byteEnable->byte_enable) Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Daniel Carvalho Reviewed-by: Nikos Nikoleris --- src/cpu/base_dyn_inst.hh | 17 +++++++++-------- src/cpu/checker/cpu.cc | 12 ++++++------ src/cpu/checker/cpu.hh | 4 ++-- src/cpu/exec_context.hh | 6 +++--- src/cpu/minor/exec_context.hh | 14 +++++++------- src/cpu/minor/lsq.cc | 10 +++++----- src/cpu/minor/lsq.hh | 2 +- src/cpu/o3/cpu.hh | 4 ++-- src/cpu/o3/lsq.hh | 12 ++++++------ src/cpu/o3/lsq_impl.hh | 6 +++--- src/cpu/simple/atomic.cc | 10 +++++----- src/cpu/simple/atomic.hh | 4 ++-- src/cpu/simple/base.hh | 6 +++--- src/cpu/simple/exec_context.hh | 18 +++++++++--------- src/cpu/simple/timing.cc | 12 ++++++------ src/cpu/simple/timing.hh | 4 ++-- 16 files changed, 71 insertions(+), 70 deletions(-) (limited to 'src') diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c228357ce..85ad54404 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -304,11 +304,11 @@ class BaseDynInst : public ExecContext, public RefCounted } Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byteEnable = std::vector()); + const std::vector& byte_enable = std::vector()); Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()); + const std::vector& byte_enable = std::vector()); Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op); @@ -963,25 +963,26 @@ template Fault BaseDynInst::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byteEnable) + const std::vector& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest( dynamic_cast(this), /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr, - byteEnable); + byte_enable); } template Fault BaseDynInst::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable) + const std::vector& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest( dynamic_cast(this), - /* st */ false, data, size, addr, flags, res, nullptr, byteEnable); + /* st */ false, data, size, addr, flags, res, nullptr, + byte_enable); } template diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 48ee05985..2f020c4a9 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -176,9 +176,9 @@ CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size, Fault CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, - const std::vector& byteEnable) + const std::vector& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); Fault fault = NoFault; bool checked_flags = false; @@ -193,7 +193,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, // Need to account for multiple accesses like the Atomic and TimingSimple while (1) { RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, - byteEnable, frag_size, + byte_enable, frag_size, size_left); predicate = (mem_req != nullptr); @@ -260,9 +260,9 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, Fault CheckerCPU::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable) + const std::vector& byte_enable) { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); Fault fault = NoFault; bool checked_flags = false; @@ -278,7 +278,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, - byteEnable, frag_size, + byte_enable, frag_size, size_left); predicate = (mem_req != nullptr); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index e50afebf5..775381c28 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -556,12 +556,12 @@ class CheckerCPU : public BaseCPU, public ExecContext Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override; Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override; Fault amoMem(Addr addr, uint8_t* data, unsigned size, diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 80f3edaee..a96ccfca3 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -236,7 +236,7 @@ class ExecContext { */ virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) { panic("ExecContext::readMem() should be overridden\n"); } @@ -250,7 +250,7 @@ class ExecContext { */ virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) { panic("ExecContext::initiateMemRead() should be overridden\n"); } @@ -261,7 +261,7 @@ class ExecContext { */ virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()) = 0; /** diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 9b347b225..4cc41c6c8 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -113,23 +113,23 @@ class ExecContext : public ::ExecContext Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) - override + const std::vector& byte_enable = + std::vector()) override { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return execute.getLSQ().pushRequest(inst, true /* load */, nullptr, - size, addr, flags, nullptr, nullptr, byteEnable); + size, addr, flags, nullptr, nullptr, byte_enable); } Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override { - assert(byteEnable.empty() || byteEnable.size() == size); + assert(byte_enable.empty() || byte_enable.size() == size); return execute.getLSQ().pushRequest(inst, false /* store */, data, - size, addr, flags, res, nullptr, byteEnable); + size, addr, flags, res, nullptr, byte_enable); } Fault diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index 629d89dc6..dea776c9e 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -295,9 +295,9 @@ LSQ::SingleDataRequest::startAddrTranslation() ThreadContext *thread = port.cpu.getContext( inst->id.threadId); - const auto &byteEnable = request->getByteEnable(); - if (byteEnable.size() == 0 || - isAnyActiveElement(byteEnable.cbegin(), byteEnable.cend())) { + const auto &byte_enable = request->getByteEnable(); + if (byte_enable.size() == 0 || + isAnyActiveElement(byte_enable.cbegin(), byte_enable.cend())) { port.numAccessesInDTLB++; setState(LSQ::LSQRequest::InTranslation); @@ -1574,7 +1574,7 @@ Fault LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector& byteEnable) + const std::vector& byte_enable) { assert(inst->translationFault == NoFault || inst->inLSQ); @@ -1636,7 +1636,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, addr, size, flags, cpu.dataMasterId(), /* I've no idea why we need the PC, but give it */ inst->pc.instAddr(), std::move(amo_op)); - request->request->setByteEnable(byteEnable); + request->request->setByteEnable(byte_enable); requests.push(request); inst->inLSQ = true; diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh index c4baad826..6b982083c 100644 --- a/src/cpu/minor/lsq.hh +++ b/src/cpu/minor/lsq.hh @@ -709,7 +709,7 @@ class LSQ : public Named Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()); /** Push a predicate failed-representing request into the queues just diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 7c0ea5166..a129fa13d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -714,12 +714,12 @@ class FullO3CPU : public BaseO3CPU Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()) { return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, - flags, res, std::move(amo_op), byteEnable); + flags, res, std::move(amo_op), byte_enable); } /** CPU read function, forwards read to LSQ. */ diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index ca92790b8..6db005cb3 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -406,16 +406,16 @@ class LSQ */ void addRequest(Addr addr, unsigned size, - const std::vector& byteEnable) + const std::vector& byte_enable) { - if (byteEnable.empty() || - isAnyActiveElement(byteEnable.begin(), byteEnable.end())) { + if (byte_enable.empty() || + isAnyActiveElement(byte_enable.begin(), byte_enable.end())) { auto request = std::make_shared(_inst->getASID(), addr, size, _flags, _inst->masterId(), _inst->instAddr(), _inst->contextId(), std::move(_amo_op)); - if (!byteEnable.empty()) { - request->setByteEnable(byteEnable); + if (!byte_enable.empty()) { + request->setByteEnable(byte_enable); } _requests.push_back(request); } @@ -1040,7 +1040,7 @@ class LSQ Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector& byteEnable); + const std::vector& byte_enable); /** The CPU pointer. */ O3CPU *cpu; diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index d7dc618a2..e85dcb96a 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -688,7 +688,7 @@ Fault LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector& byteEnable) + const std::vector& byte_enable) { // This comming request can be either load, store or atomic. // Atomic request has a corresponding pointer to its atomic memory @@ -720,8 +720,8 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, size, flags, data, res, std::move(amo_op)); } assert(req); - if (!byteEnable.empty()) { - req->_byteEnable = byteEnable; + if (!byte_enable.empty()) { + req->_byteEnable = byte_enable; } inst->setRequest(); req->taskId(cpu->taskId()); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 9052cee2e..3e3ba41b3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -371,7 +371,7 @@ AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr, Fault AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, Request::Flags flags, - const std::vector& byteEnable) + const std::vector& byte_enable) { SimpleExecContext& t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -394,7 +394,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, while (1) { predicate = genMemFragmentRequest(req, frag_addr, size, flags, - byteEnable, frag_size, size_left); + byte_enable, frag_size, size_left); // translate to physical address if (predicate) { @@ -453,7 +453,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, Fault AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable) + const std::vector& byte_enable) { SimpleExecContext& t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -485,7 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, while (1) { predicate = genMemFragmentRequest(req, frag_addr, size, flags, - byteEnable, frag_size, size_left); + byte_enable, frag_size, size_left); // translate to physical address if (predicate) @@ -541,7 +541,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, if (fault != NoFault || size_left == 0) { if (req->isLockedRMW() && fault == NoFault) { - assert(byteEnable.empty()); + assert(byte_enable.empty()); locked = false; } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 121cecd65..8fd950527 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -218,12 +218,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override; Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override; Fault amoMem(Addr addr, uint8_t* data, unsigned size, diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index f8e534c85..32c20a1a0 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -144,19 +144,19 @@ class BaseSimpleCPU : public BaseCPU virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()) { panic("readMem() is not implemented\n"); } virtual Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()) { panic("initiateMemRead() is not implemented\n"); } virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr, Request::Flags flags, uint64_t* res, - const std::vector& byteEnable = + const std::vector& byte_enable = std::vector()) { panic("writeMem() is not implemented\n"); } diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 8e4aa3961..04be1a016 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -437,31 +437,31 @@ class SimpleExecContext : public ExecContext { Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override { - assert(byteEnable.empty() || byteEnable.size() == size); - return cpu->readMem(addr, data, size, flags, byteEnable); + assert(byte_enable.empty() || byte_enable.size() == size); + return cpu->readMem(addr, data, size, flags, byte_enable); } Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override { - assert(byteEnable.empty() || byteEnable.size() == size); - return cpu->initiateMemRead(addr, size, flags, byteEnable); + assert(byte_enable.empty() || byte_enable.size() == size); + return cpu->initiateMemRead(addr, size, flags, byte_enable); } Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override { - assert(byteEnable.empty() || byteEnable.size() == size); - return cpu->writeMem(data, size, addr, flags, res, byteEnable); + assert(byte_enable.empty() || byte_enable.size() == size); + return cpu->writeMem(data, size, addr, flags, res, byte_enable); } Fault amoMem(Addr addr, uint8_t *data, unsigned int size, diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index d05eece27..6487ffa97 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -418,7 +418,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, Fault TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byteEnable) + const std::vector& byte_enable) { SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -435,8 +435,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, RequestPtr req = std::make_shared( asid, addr, size, flags, dataMasterId(), pc, thread->contextId()); - if (!byteEnable.empty()) { - req->setByteEnable(byteEnable); + if (!byte_enable.empty()) { + req->setByteEnable(byte_enable); } req->taskId(taskId()); @@ -496,7 +496,7 @@ TimingSimpleCPU::handleWritePacket() Fault TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable) + const std::vector& byte_enable) { SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -521,8 +521,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, RequestPtr req = std::make_shared( asid, addr, size, flags, dataMasterId(), pc, thread->contextId()); - if (!byteEnable.empty()) { - req->setByteEnable(byteEnable); + if (!byte_enable.empty()) { + req->setByteEnable(byte_enable); } req->taskId(taskId()); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 27faa177a..cab4253fb 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -284,12 +284,12 @@ class TimingSimpleCPU : public BaseSimpleCPU Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byteEnable =std::vector()) + const std::vector& byte_enable =std::vector()) override; Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byteEnable = std::vector()) + const std::vector& byte_enable = std::vector()) override; Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, -- cgit v1.2.3