From 4f0f217c1b6a8c888ff8a1c60d1eb36cbdf14490 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 26 May 2007 18:15:22 -0700 Subject: Get rid of GNU libelf and its autoconf nastiness and replace it with FreeBSD's implementation --HG-- extra : convert_revision : ef9c4551b9a6b54b76a89f286ff9804c55790621 --- src/base/loader/elf_object.cc | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) (limited to 'src') diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 8f157da28..f76ea593b 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -31,23 +31,14 @@ #include -// Because of the -Wundef flag we have to do this -#define __LIBELF_INTERNAL__ 0 -#define __LIBELF_NEED_LINK_H 0 -#define __LIBELF_SYMBOL_VERSIONS 0 - #include "gelf.h" #include "base/loader/elf_object.hh" -#include "base/misc.hh" - #include "base/loader/symtab.hh" - +#include "base/misc.hh" #include "base/trace.hh" // for DPRINTF - #include "sim/byteswap.hh" - using namespace std; ObjectFile * -- cgit v1.2.3 From 35147170f91ccbc73d3e75440a5301f758e54dfc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 27 May 2007 19:21:17 -0700 Subject: Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321 --- src/arch/alpha/AlphaSystem.py | 52 +++++++ src/arch/alpha/AlphaTLB.py | 42 ++++++ src/arch/alpha/SConscript | 3 + src/arch/sparc/SConscript | 3 + src/arch/sparc/SparcSystem.py | 74 ++++++++++ src/arch/sparc/SparcTLB.py | 42 ++++++ src/cpu/BaseCPU.py | 106 ++++++++++++++ src/cpu/FuncUnit.py | 46 ++++++ src/cpu/IntrControl.py | 34 +++++ src/cpu/SConscript | 5 + src/cpu/memtest/MemTest.py | 52 +++++++ src/cpu/memtest/SConscript | 2 + src/cpu/o3/FUPool.py | 40 ++++++ src/cpu/o3/FuncUnitConfig.py | 69 +++++++++ src/cpu/o3/O3CPU.py | 153 ++++++++++++++++++++ src/cpu/o3/O3Checker.py | 43 ++++++ src/cpu/o3/SConscript | 5 + src/cpu/ozone/OzoneCPU.py | 127 +++++++++++++++++ src/cpu/ozone/OzoneChecker.py | 43 ++++++ src/cpu/ozone/SConscript | 4 + src/cpu/ozone/SimpleOzoneCPU.py | 115 +++++++++++++++ src/cpu/simple/AtomicSimpleCPU.py | 43 ++++++ src/cpu/simple/SConscript | 2 + src/cpu/simple/TimingSimpleCPU.py | 41 ++++++ src/dev/BadDevice.py | 34 +++++ src/dev/Device.py | 71 ++++++++++ src/dev/DiskImage.py | 44 ++++++ src/dev/Ethernet.py | 199 ++++++++++++++++++++++++++ src/dev/Ide.py | 68 +++++++++ src/dev/Pci.py | 87 ++++++++++++ src/dev/Platform.py | 35 +++++ src/dev/SConscript | 11 ++ src/dev/SimConsole.py | 39 ++++++ src/dev/SimpleDisk.py | 35 +++++ src/dev/Uart.py | 45 ++++++ src/dev/alpha/AlphaConsole.py | 38 +++++ src/dev/alpha/SConscript | 3 + src/dev/alpha/Tsunami.py | 123 ++++++++++++++++ src/dev/sparc/SConscript | 2 + src/dev/sparc/T1000.py | 134 ++++++++++++++++++ src/mem/Bridge.py | 44 ++++++ src/mem/Bus.py | 49 +++++++ src/mem/MemObject.py | 34 +++++ src/mem/PhysicalMemory.py | 57 ++++++++ src/mem/SConscript | 5 + src/mem/cache/BaseCache.py | 91 ++++++++++++ src/mem/cache/SConscript | 2 + src/mem/cache/coherence/CoherenceProtocol.py | 8 ++ src/mem/cache/coherence/SConscript | 2 + src/mem/cache/tags/Repl.py | 11 ++ src/mem/cache/tags/SConscript | 1 + src/python/SConscript | 51 ------- src/python/m5/objects/AlphaConsole.py | 10 -- src/python/m5/objects/AlphaTLB.py | 14 -- src/python/m5/objects/BadDevice.py | 6 - src/python/m5/objects/BaseCPU.py | 73 ---------- src/python/m5/objects/BaseCache.py | 63 --------- src/python/m5/objects/Bridge.py | 16 --- src/python/m5/objects/Bus.py | 19 --- src/python/m5/objects/CoherenceProtocol.py | 8 -- src/python/m5/objects/Device.py | 43 ------ src/python/m5/objects/DiskImage.py | 16 --- src/python/m5/objects/Ethernet.py | 200 --------------------------- src/python/m5/objects/FUPool.py | 12 -- src/python/m5/objects/FuncUnit.py | 18 --- src/python/m5/objects/FuncUnitConfig.py | 41 ------ src/python/m5/objects/Ide.py | 40 ------ src/python/m5/objects/IntrControl.py | 6 - src/python/m5/objects/MemObject.py | 6 - src/python/m5/objects/MemTest.py | 24 ---- src/python/m5/objects/O3CPU.py | 123 ---------------- src/python/m5/objects/OzoneCPU.py | 95 ------------- src/python/m5/objects/Pci.py | 59 -------- src/python/m5/objects/PhysicalMemory.py | 29 ---- src/python/m5/objects/Platform.py | 7 - src/python/m5/objects/Process.py | 36 ----- src/python/m5/objects/Repl.py | 11 -- src/python/m5/objects/Root.py | 6 - src/python/m5/objects/SimConsole.py | 11 -- src/python/m5/objects/SimpleDisk.py | 7 - src/python/m5/objects/SimpleOzoneCPU.py | 87 ------------ src/python/m5/objects/SparcTLB.py | 14 -- src/python/m5/objects/System.py | 68 --------- src/python/m5/objects/T1000.py | 106 -------------- src/python/m5/objects/Tsunami.py | 95 ------------- src/python/m5/objects/Uart.py | 17 --- src/sim/Process.py | 51 +++++++ src/sim/Root.py | 34 +++++ src/sim/SConscript | 5 + src/sim/System.py | 48 +++++++ 90 files changed, 2556 insertions(+), 1437 deletions(-) create mode 100644 src/arch/alpha/AlphaSystem.py create mode 100644 src/arch/alpha/AlphaTLB.py create mode 100644 src/arch/sparc/SparcSystem.py create mode 100644 src/arch/sparc/SparcTLB.py create mode 100644 src/cpu/BaseCPU.py create mode 100644 src/cpu/FuncUnit.py create mode 100644 src/cpu/IntrControl.py create mode 100644 src/cpu/memtest/MemTest.py create mode 100644 src/cpu/o3/FUPool.py create mode 100644 src/cpu/o3/FuncUnitConfig.py create mode 100644 src/cpu/o3/O3CPU.py create mode 100644 src/cpu/o3/O3Checker.py create mode 100644 src/cpu/ozone/OzoneCPU.py create mode 100644 src/cpu/ozone/OzoneChecker.py create mode 100644 src/cpu/ozone/SimpleOzoneCPU.py create mode 100644 src/cpu/simple/AtomicSimpleCPU.py create mode 100644 src/cpu/simple/TimingSimpleCPU.py create mode 100644 src/dev/BadDevice.py create mode 100644 src/dev/Device.py create mode 100644 src/dev/DiskImage.py create mode 100644 src/dev/Ethernet.py create mode 100644 src/dev/Ide.py create mode 100644 src/dev/Pci.py create mode 100644 src/dev/Platform.py create mode 100644 src/dev/SimConsole.py create mode 100644 src/dev/SimpleDisk.py create mode 100644 src/dev/Uart.py create mode 100644 src/dev/alpha/AlphaConsole.py create mode 100644 src/dev/alpha/Tsunami.py create mode 100644 src/dev/sparc/T1000.py create mode 100644 src/mem/Bridge.py create mode 100644 src/mem/Bus.py create mode 100644 src/mem/MemObject.py create mode 100644 src/mem/PhysicalMemory.py create mode 100644 src/mem/cache/BaseCache.py create mode 100644 src/mem/cache/coherence/CoherenceProtocol.py create mode 100644 src/mem/cache/tags/Repl.py delete mode 100644 src/python/m5/objects/AlphaConsole.py delete mode 100644 src/python/m5/objects/AlphaTLB.py delete mode 100644 src/python/m5/objects/BadDevice.py delete mode 100644 src/python/m5/objects/BaseCPU.py delete mode 100644 src/python/m5/objects/BaseCache.py delete mode 100644 src/python/m5/objects/Bridge.py delete mode 100644 src/python/m5/objects/Bus.py delete mode 100644 src/python/m5/objects/CoherenceProtocol.py delete mode 100644 src/python/m5/objects/Device.py delete mode 100644 src/python/m5/objects/DiskImage.py delete mode 100644 src/python/m5/objects/Ethernet.py delete mode 100644 src/python/m5/objects/FUPool.py delete mode 100644 src/python/m5/objects/FuncUnit.py delete mode 100644 src/python/m5/objects/FuncUnitConfig.py delete mode 100644 src/python/m5/objects/Ide.py delete mode 100644 src/python/m5/objects/IntrControl.py delete mode 100644 src/python/m5/objects/MemObject.py delete mode 100644 src/python/m5/objects/MemTest.py delete mode 100644 src/python/m5/objects/O3CPU.py delete mode 100644 src/python/m5/objects/OzoneCPU.py delete mode 100644 src/python/m5/objects/Pci.py delete mode 100644 src/python/m5/objects/PhysicalMemory.py delete mode 100644 src/python/m5/objects/Platform.py delete mode 100644 src/python/m5/objects/Process.py delete mode 100644 src/python/m5/objects/Repl.py delete mode 100644 src/python/m5/objects/Root.py delete mode 100644 src/python/m5/objects/SimConsole.py delete mode 100644 src/python/m5/objects/SimpleDisk.py delete mode 100644 src/python/m5/objects/SimpleOzoneCPU.py delete mode 100644 src/python/m5/objects/SparcTLB.py delete mode 100644 src/python/m5/objects/System.py delete mode 100644 src/python/m5/objects/T1000.py delete mode 100644 src/python/m5/objects/Tsunami.py delete mode 100644 src/python/m5/objects/Uart.py create mode 100644 src/sim/Process.py create mode 100644 src/sim/Root.py create mode 100644 src/sim/System.py (limited to 'src') diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py new file mode 100644 index 000000000..a19aeb763 --- /dev/null +++ b/src/arch/alpha/AlphaSystem.py @@ -0,0 +1,52 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from System import System + +class AlphaSystem(System): + type = 'AlphaSystem' + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + +class LinuxAlphaSystem(AlphaSystem): + type = 'LinuxAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class FreebsdAlphaSystem(AlphaSystem): + type = 'FreebsdAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class Tru64AlphaSystem(AlphaSystem): + type = 'Tru64AlphaSystem' + system_type = 12 + system_rev = 2<<1 diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py new file mode 100644 index 000000000..559516725 --- /dev/null +++ b/src/arch/alpha/AlphaTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class AlphaTLB(SimObject): + type = 'AlphaTLB' + abstract = True + size = Param.Int("TLB size") + +class AlphaDTB(AlphaTLB): + type = 'AlphaDTB' + size = 64 + +class AlphaITB(AlphaTLB): + type = 'AlphaITB' + size = 48 diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 61611e9f6..2d59180c4 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('AlphaSystem.py') + SimObject('AlphaTLB.py') + Source('arguments.cc') Source('ev5.cc') Source('idle_event.cc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index e342c79cf..c9dbb8cf2 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('SparcSystem.py') + SimObject('SparcTLB.py') + Source('arguments.cc') Source('pagetable.cc') Source('stacktrace.cc') diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py new file mode 100644 index 000000000..2e65f640d --- /dev/null +++ b/src/arch/sparc/SparcSystem.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * + +from PhysicalMemory import * +from System import System + +class SparcSystem(System): + type = 'SparcSystem' + _rom_base = 0xfff0000000 + _nvram_base = 0x1f11000000 + _hypervisor_desc_base = 0x1f12080000 + _partition_desc_base = 0x1f12000000 + # ROM for OBP/Reset/Hypervisor + rom = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_rom_base, size='8MB')), + "Memory to hold the ROM data") + # nvram + nvram = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')), + "Memory to hold the nvram data") + # hypervisor description + hypervisor_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')), + "Memory to hold the hypervisor description") + # partition description + partition_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')), + "Memory to hold the partition description") + + reset_addr = Param.Addr(_rom_base, "Address to load ROM at") + hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, + "Address to load hypervisor at") + openboot_addr = Param.Addr(Addr('512kB') + _rom_base, + "Address to load openboot at") + nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") + hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, + "Address for the hypervisor description") + partition_desc_addr = Param.Addr(_partition_desc_base, + "Address for the partition description") + + reset_bin = Param.String("file that contains the reset code") + hypervisor_bin = Param.String("file that contains the hypervisor code") + openboot_bin = Param.String("file that contains the openboot code") + nvram_bin = Param.String("file that contains the contents of nvram") + hypervisor_desc_bin = Param.String("file that contains the hypervisor description") + partition_desc_bin = Param.String("file that contains the partition description") + diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py new file mode 100644 index 000000000..30e5ebb08 --- /dev/null +++ b/src/arch/sparc/SparcTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.SimObject import SimObject +from m5.params import * +class SparcTLB(SimObject): + type = 'SparcTLB' + abstract = True + size = Param.Int("TLB size") + +class SparcDTB(SparcTLB): + type = 'SparcDTB' + size = 64 + +class SparcITB(SparcTLB): + type = 'SparcITB' + size = 64 diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py new file mode 100644 index 000000000..6c2aace51 --- /dev/null +++ b/src/cpu/BaseCPU.py @@ -0,0 +1,106 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env +from Bus import Bus +import sys + +if build_env['FULL_SYSTEM']: + if build_env['TARGET_ISA'] == 'alpha': + from AlphaTLB import AlphaDTB, AlphaITB + + if build_env['TARGET_ISA'] == 'sparc': + from SparcTLB import SparcDTB, SparcITB + +class BaseCPU(SimObject): + type = 'BaseCPU' + abstract = True + + system = Param.System(Parent.any, "system object") + cpu_id = Param.Int("CPU identifier") + + if build_env['FULL_SYSTEM']: + do_quiesce = Param.Bool(True, "enable quiesce instructions") + do_checkpoint_insts = Param.Bool(True, + "enable checkpoint pseudo instructions") + do_statistics_insts = Param.Bool(True, + "enable statistics pseudo instructions") + + if build_env['TARGET_ISA'] == 'sparc': + dtb = Param.SparcDTB(SparcDTB(), "Data TLB") + itb = Param.SparcITB(SparcITB(), "Instruction TLB") + elif build_env['TARGET_ISA'] == 'alpha': + dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") + itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") + else: + print "Unknown architecture, can't pick TLBs" + sys.exit(1) + else: + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + progress_interval = Param.Tick(0, + "interval to print out the progress message") + + defer_registration = Param.Bool(False, + "defer registration with system (for sampling)") + + clock = Param.Clock('1t', "clock speed") + phase = Param.Latency('0ns', "clock phase") + + _mem_ports = [] + + def connectMemPorts(self, bus): + for p in self._mem_ports: + exec('self.%s = bus.port' % p) + + def addPrivateSplitL1Caches(self, ic, dc): + assert(len(self._mem_ports) == 2) + self.icache = ic + self.dcache = dc + self.icache_port = ic.cpu_side + self.dcache_port = dc.cpu_side + self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] + + def addTwoLevelCacheHierarchy(self, ic, dc, l2c): + self.addPrivateSplitL1Caches(ic, dc) + self.toL2Bus = Bus() + self.connectMemPorts(self.toL2Bus) + self.l2cache = l2c + self.l2cache.cpu_side = self.toL2Bus.port + self._mem_ports = ['l2cache.mem_side'] diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py new file mode 100644 index 000000000..541bdbd83 --- /dev/null +++ b/src/cpu/FuncUnit.py @@ -0,0 +1,46 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * + +class OpType(Enum): + vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', + 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] + +class OpDesc(SimObject): + type = 'OpDesc' + issueLat = Param.Int(1, "cycles until another can be issued") + opClass = Param.OpType("type of operation") + opLat = Param.Int(1, "cycles until result is available") + +class FUDesc(SimObject): + type = 'FUDesc' + count = Param.Int("number of these FU's available") + opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py new file mode 100644 index 000000000..eb4b1696b --- /dev/null +++ b/src/cpu/IntrControl.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class IntrControl(SimObject): + type = 'IntrControl' + sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 1c2278f6f..cce13a072 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -103,6 +103,9 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) # and one of these are not being used. CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] +SimObject('BaseCPU.py') +SimObject('FuncUnit.py') + Source('activity.cc') Source('base.cc') Source('cpuevent.cc') @@ -116,6 +119,8 @@ Source('simple_thread.cc') Source('thread_state.cc') if env['FULL_SYSTEM']: + SimObject('IntrControl.py') + Source('intr_control.cc') Source('profile.cc') diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py new file mode 100644 index 000000000..381519972 --- /dev/null +++ b/src/cpu/memtest/MemTest.py @@ -0,0 +1,52 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env + +class MemTest(SimObject): + type = 'MemTest' + max_loads = Param.Counter("number of loads to execute") + atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") + memory_size = Param.Int(65536, "memory size") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") + + test = Port("Port to the memory system to test") + functional = Port("Port to the functional memory used for verification") diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript index 7b4d6d2c5..1f6621a4c 100644 --- a/src/cpu/memtest/SConscript +++ b/src/cpu/memtest/SConscript @@ -31,4 +31,6 @@ Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('MemTest.py') + Source('memtest.cc') diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py new file mode 100644 index 000000000..4f07f9867 --- /dev/null +++ b/src/cpu/o3/FUPool.py @@ -0,0 +1,40 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * +from FuncUnitConfig import * + +class FUPool(SimObject): + type = 'FUPool' + FUList = VectorParam.FUDesc("list of FU's for this pool") + +class DefaultFUPool(FUPool): + FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), + WritePort(), RdWrPort(), IprPort() ] diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py new file mode 100644 index 000000000..954381f86 --- /dev/null +++ b/src/cpu/o3/FuncUnitConfig.py @@ -0,0 +1,69 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * + +class IntALU(FUDesc): + opList = [ OpDesc(opClass='IntAlu') ] + count = 6 + +class IntMultDiv(FUDesc): + opList = [ OpDesc(opClass='IntMult', opLat=3), + OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] + count=2 + +class FP_ALU(FUDesc): + opList = [ OpDesc(opClass='FloatAdd', opLat=2), + OpDesc(opClass='FloatCmp', opLat=2), + OpDesc(opClass='FloatCvt', opLat=2) ] + count = 4 + +class FP_MultDiv(FUDesc): + opList = [ OpDesc(opClass='FloatMult', opLat=4), + OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), + OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] + count = 2 + +class ReadPort(FUDesc): + opList = [ OpDesc(opClass='MemRead') ] + count = 0 + +class WritePort(FUDesc): + opList = [ OpDesc(opClass='MemWrite') ] + count = 0 + +class RdWrPort(FUDesc): + opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] + count = 4 + +class IprPort(FUDesc): + opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] + count = 1 + diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py new file mode 100644 index 000000000..e031faefa --- /dev/null +++ b/src/cpu/o3/O3CPU.py @@ -0,0 +1,153 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.params import * +from m5.proxy import * +from m5 import build_env +from BaseCPU import BaseCPU +from FUPool import * + +if build_env['USE_CHECKER']: + from O3Checker import O3Checker + +class DerivO3CPU(BaseCPU): + type = 'DerivO3CPU' + activity = Param.Unsigned(0, "Initial count") + numThreads = Param.Unsigned(1, "number of HW thread contexts") + + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + if build_env['USE_CHECKER']: + if not build_env['FULL_SYSTEM']: + checker = Param.BaseCPU(O3Checker(workload=Parent.workload, + exitOnError=False, + updateOnError=True, + warnOnlyOnLoadError=False), + "checker") + else: + checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, + warnOnlyOnLoadError=False), "checker") + checker.itb = Parent.itb + checker.dtb = Parent.dtb + + cachePorts = Param.Unsigned("Cache Ports") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] + + decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") + renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") + iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") + fetchWidth = Param.Unsigned(8, "Fetch width") + + renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") + iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") + decodeWidth = Param.Unsigned(8, "Decode width") + + iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") + decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") + renameWidth = Param.Unsigned(8, "Rename width") + + commitToIEWDelay = Param.Unsigned(1, "Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned(2, "Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " + "to the IEW stage)") + dispatchWidth = Param.Unsigned(8, "Dispatch width") + issueWidth = Param.Unsigned(8, "Issue width") + wbWidth = Param.Unsigned(8, "Writeback width") + wbDepth = Param.Unsigned(1, "Writeback depth") + fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") + + iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") + commitWidth = Param.Unsigned(8, "Commit width") + squashWidth = Param.Unsigned(8, "Squash width") + trapLatency = Param.Tick(13, "Trap latency") + fetchTrapLatency = Param.Tick(1, "Fetch trap latency") + + backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") + forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") + + predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") + localPredictorSize = Param.Unsigned(2048, "Size of local predictor") + localCtrBits = Param.Unsigned(2, "Bits per counter") + localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") + localHistoryBits = Param.Unsigned(11, "Bits for the local history") + globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") + globalCtrBits = Param.Unsigned(2, "Bits per counter") + globalHistoryBits = Param.Unsigned(13, "Bits of history") + choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") + choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") + + BTBEntries = Param.Unsigned(4096, "Number of BTB entries") + BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") + + RASSize = Param.Unsigned(16, "RAS size") + + LQEntries = Param.Unsigned(32, "Number of load queue entries") + SQEntries = Param.Unsigned(32, "Number of store queue entries") + LFSTSize = Param.Unsigned(1024, "Last fetched store table size") + SSITSize = Param.Unsigned(1024, "Store set ID table size") + + numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); + + numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") + numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + + smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") + smtFetchPolicy = Param.String("SMT Fetch policy") + smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") + smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String("SMT IQ Sharing Policy") + smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String("SMT ROB Sharing Policy") + smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String("SMT Commit Policy") + + def addPrivateSplitL1Caches(self, ic, dc): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + self.icache.tgts_per_mshr = 20 + self.dcache.tgts_per_mshr = 20 diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py new file mode 100644 index 000000000..43a71d67b --- /dev/null +++ b/src/cpu/o3/O3Checker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class O3Checker(BaseCPU): + type = 'O3Checker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index bb1dfb613..a1af620be 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -33,6 +33,10 @@ import sys Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('FUPool.py') + SimObject('FuncUnitConfig.py') + SimObject('O3CPU.py') + Source('base_dyn_inst.cc') Source('bpred_unit.cc') Source('commit.cc') @@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) if env['USE_CHECKER']: + SimObject('m5/objects/O3Checker.py') Source('checker_builder.cc') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py new file mode 100644 index 000000000..b9cfb448f --- /dev/null +++ b/src/cpu/ozone/OzoneCPU.py @@ -0,0 +1,127 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +if build_env['USE_CHECKER']: + from OzoneChecker import OzoneChecker + +class DerivOzoneCPU(BaseCPU): + type = 'DerivOzoneCPU' + + numThreads = Param.Unsigned("number of HW thread contexts") + + if build_env['USE_CHECKER']: + checker = Param.BaseCPU("Checker CPU") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + + width = Param.Unsigned("Width") + frontEndWidth = Param.Unsigned("Front end width") + frontEndLatency = Param.Unsigned("Front end latency") + backEndWidth = Param.Unsigned("Back end width") + backEndSquashLatency = Param.Unsigned("Back end squash latency") + backEndLatency = Param.Unsigned("Back end latency") + maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size") + maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations") + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") + renameToFetchDelay = Param.Unsigned("Rename to fetch delay") + iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned("Commit to fetch delay") + fetchWidth = Param.Unsigned("Fetch width") + + renameToDecodeDelay = Param.Unsigned("Rename to decode delay") + iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned("Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") + decodeWidth = Param.Unsigned("Decode width") + + iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned("Commit to rename delay") + decodeToRenameDelay = Param.Unsigned("Decode to rename delay") + renameWidth = Param.Unsigned("Rename width") + + commitToIEWDelay = Param.Unsigned("Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned("Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + "to the IEW stage)") + issueWidth = Param.Unsigned("Issue width") + executeWidth = Param.Unsigned("Execute width") + executeIntWidth = Param.Unsigned("Integer execute width") + executeFloatWidth = Param.Unsigned("Floating point execute width") + executeBranchWidth = Param.Unsigned("Branch execute width") + executeMemoryWidth = Param.Unsigned("Memory execute width") + + iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") + commitWidth = Param.Unsigned("Commit width") + squashWidth = Param.Unsigned("Squash width") + + predType = Param.String("Type of branch predictor ('local', 'tournament')") + localPredictorSize = Param.Unsigned("Size of local predictor") + localCtrBits = Param.Unsigned("Bits per counter") + localHistoryTableSize = Param.Unsigned("Size of local history table") + localHistoryBits = Param.Unsigned("Bits for the local history") + globalPredictorSize = Param.Unsigned("Size of global predictor") + globalCtrBits = Param.Unsigned("Bits per counter") + globalHistoryBits = Param.Unsigned("Bits of history") + choicePredictorSize = Param.Unsigned("Size of choice predictor") + choiceCtrBits = Param.Unsigned("Bits of choice counters") + + BTBEntries = Param.Unsigned("Number of BTB entries") + BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") + + RASSize = Param.Unsigned("RAS size") + + LQEntries = Param.Unsigned("Number of load queue entries") + SQEntries = Param.Unsigned("Number of store queue entries") + lsqLimits = Param.Bool(True, "LSQ size limits dispatch") + LFSTSize = Param.Unsigned("Last fetched store table size") + SSITSize = Param.Unsigned("Store set ID table size") + + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned("Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned("Number of instruction queue entries") + numROBEntries = Param.Unsigned("Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py new file mode 100644 index 000000000..f20b8770e --- /dev/null +++ b/src/cpu/ozone/OzoneChecker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class OzoneChecker(BaseCPU): + type = 'OzoneChecker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index 4a040684a..601e80a72 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -31,6 +31,9 @@ Import('*') if 'OzoneCPU' in env['CPU_MODELS']: + SimObject('OzoneCPU.py') + SimObject('SimpleOzoneCPU.py') + need_bp_unit = True Source('base_dyn_inst.cc') Source('bpred_unit.cc') @@ -42,4 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_lsq.cc') Source('rename_table.cc') if env['USE_CHECKER']: + SimObject('m5/objects/OzoneChecker.py') Source('checker_builder.cc') diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py new file mode 100644 index 000000000..93603092b --- /dev/null +++ b/src/cpu/ozone/SimpleOzoneCPU.py @@ -0,0 +1,115 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class SimpleOzoneCPU(BaseCPU): + type = 'SimpleOzoneCPU' + + numThreads = Param.Unsigned("number of HW thread contexts") + + if not build_env['FULL_SYSTEM']: + mem = Param.FunctionalMemory(NULL, "memory") + + width = Param.Unsigned("Width") + frontEndWidth = Param.Unsigned("Front end width") + backEndWidth = Param.Unsigned("Back end width") + backEndSquashLatency = Param.Unsigned("Back end squash latency") + backEndLatency = Param.Unsigned("Back end latency") + maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size") + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") + renameToFetchDelay = Param.Unsigned("Rename to fetch delay") + iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned("Commit to fetch delay") + fetchWidth = Param.Unsigned("Fetch width") + + renameToDecodeDelay = Param.Unsigned("Rename to decode delay") + iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned("Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") + decodeWidth = Param.Unsigned("Decode width") + + iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned("Commit to rename delay") + decodeToRenameDelay = Param.Unsigned("Decode to rename delay") + renameWidth = Param.Unsigned("Rename width") + + commitToIEWDelay = Param.Unsigned("Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned("Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + "to the IEW stage)") + issueWidth = Param.Unsigned("Issue width") + executeWidth = Param.Unsigned("Execute width") + executeIntWidth = Param.Unsigned("Integer execute width") + executeFloatWidth = Param.Unsigned("Floating point execute width") + executeBranchWidth = Param.Unsigned("Branch execute width") + executeMemoryWidth = Param.Unsigned("Memory execute width") + + iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") + commitWidth = Param.Unsigned("Commit width") + squashWidth = Param.Unsigned("Squash width") + + localPredictorSize = Param.Unsigned("Size of local predictor") + localCtrBits = Param.Unsigned("Bits per counter") + localHistoryTableSize = Param.Unsigned("Size of local history table") + localHistoryBits = Param.Unsigned("Bits for the local history") + globalPredictorSize = Param.Unsigned("Size of global predictor") + globalCtrBits = Param.Unsigned("Bits per counter") + globalHistoryBits = Param.Unsigned("Bits of history") + choicePredictorSize = Param.Unsigned("Size of choice predictor") + choiceCtrBits = Param.Unsigned("Bits of choice counters") + + BTBEntries = Param.Unsigned("Number of BTB entries") + BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") + + RASSize = Param.Unsigned("RAS size") + + LQEntries = Param.Unsigned("Number of load queue entries") + SQEntries = Param.Unsigned("Number of store queue entries") + LFSTSize = Param.Unsigned("Last fetched store table size") + SSITSize = Param.Unsigned("Store set ID table size") + + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned("Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned("Number of instruction queue entries") + numROBEntries = Param.Unsigned("Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py new file mode 100644 index 000000000..e97f059c1 --- /dev/null +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class AtomicSimpleCPU(BaseCPU): + type = 'AtomicSimpleCPU' + width = Param.Int(1, "CPU width") + simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index 9a6a80473..ccccab2b5 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -33,10 +33,12 @@ Import('*') need_simple_base = False if 'AtomicSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('AtomicSimpleCPU.py') Source('atomic.cc') if 'TimingSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('TimingSimpleCPU.py') Source('timing.cc') if need_simple_base: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py new file mode 100644 index 000000000..2fcde175c --- /dev/null +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -0,0 +1,41 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class TimingSimpleCPU(BaseCPU): + type = 'TimingSimpleCPU' + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py new file mode 100644 index 000000000..4fc592184 --- /dev/null +++ b/src/dev/BadDevice.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from Device import BasicPioDevice + +class BadDevice(BasicPioDevice): + type = 'BadDevice' + devicename = Param.String("Name of device to error on") diff --git a/src/dev/Device.py b/src/dev/Device.py new file mode 100644 index 000000000..adf262f26 --- /dev/null +++ b/src/dev/Device.py @@ -0,0 +1,71 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from MemObject import MemObject + +class PioDevice(MemObject): + type = 'PioDevice' + abstract = True + pio = Port("Programmed I/O port") + platform = Param.Platform(Parent.any, "Platform this device is part of") + system = Param.System(Parent.any, "System this device is part of") + +class BasicPioDevice(PioDevice): + type = 'BasicPioDevice' + abstract = True + pio_addr = Param.Addr("Device Address") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") + +class DmaDevice(PioDevice): + type = 'DmaDevice' + abstract = True + dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + + +class IsaFake(BasicPioDevice): + type = 'IsaFake' + pio_size = Param.Addr(0x8, "Size of address range") + ret_data8 = Param.UInt8(0xFF, "Default data to return") + ret_data16 = Param.UInt16(0xFFFF, "Default data to return") + ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") + ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") + ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") + update_data = Param.Bool(False, "Update the data that is returned on writes") + warn_access = Param.String("", "String to print when device is accessed") + +class BadAddr(IsaFake): + ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") + + diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py new file mode 100644 index 000000000..af2407458 --- /dev/null +++ b/src/dev/DiskImage.py @@ -0,0 +1,44 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class DiskImage(SimObject): + type = 'DiskImage' + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(False, "read only image") + +class RawDiskImage(DiskImage): + type = 'RawDiskImage' + +class CowDiskImage(DiskImage): + type = 'CowDiskImage' + child = Param.DiskImage(RawDiskImage(read_only=True), + "child image") + table_size = Param.Int(65536, "initial table size") diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py new file mode 100644 index 000000000..e81862a96 --- /dev/null +++ b/src/dev/Ethernet.py @@ -0,0 +1,199 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from Pci import PciDevice, PciConfigData + +class EtherInt(SimObject): + type = 'EtherInt' + abstract = True + peer = Param.EtherInt(NULL, "peer interface") + +class EtherLink(SimObject): + type = 'EtherLink' + int1 = Param.EtherInt("interface 1") + int2 = Param.EtherInt("interface 2") + delay = Param.Latency('0us', "packet transmit delay") + delay_var = Param.Latency('0ns', "packet transmit delay variability") + speed = Param.NetworkBandwidth('1Gbps', "link speed") + dump = Param.EtherDump(NULL, "dump object") + +class EtherBus(SimObject): + type = 'EtherBus' + loopback = Param.Bool(True, "send packet back to the sending interface") + dump = Param.EtherDump(NULL, "dump object") + speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") + +class EtherTap(EtherInt): + type = 'EtherTap' + bufsz = Param.Int(10000, "tap buffer size") + dump = Param.EtherDump(NULL, "dump object") + port = Param.UInt16(3500, "tap port") + +class EtherDump(SimObject): + type = 'EtherDump' + file = Param.String("dump file") + maxlen = Param.Int(96, "max portion of packet data to dump") + +class IGbE(PciDevice): + type = 'IGbE' + hardware_address = Param.String("Ethernet Hardware Address") + use_flow_control = Param.Bool(False, + "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") + rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") + tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") + rx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") + tx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") + clock = Param.Clock('500MHz', "Clock speed of the device") + +class IGbEPciData(PciConfigData): + VendorID = 0x8086 + DeviceID = 0x1075 + SubsystemID = 0x1008 + SubsystemVendorID = 0x8086 + Status = 0x0000 + SubClassCode = 0x00 + ClassCode = 0x02 + ProgIF = 0x00 + BAR0 = 0x00000000 + BAR1 = 0x00000000 + BAR2 = 0x00000000 + BAR3 = 0x00000000 + BAR4 = 0x00000000 + BAR5 = 0x00000000 + MaximumLatency = 0x00 + MinimumGrant = 0xff + InterruptLine = 0x1e + InterruptPin = 0x01 + BAR0Size = '128kB' + +class IGbEInt(EtherInt): + type = 'IGbEInt' + device = Param.IGbE("Ethernet device of this interface") + + + +class EtherDevBase(PciDevice): + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + clock = Param.Clock('0ns', "State machine processor frequency") + + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") + tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + intr_delay = Param.Latency('10us', "Interrupt propagation delay") + rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") + tx_thread = Param.Bool(False, "dedicated kernel threads for receive") + rss = Param.Bool(False, "Receive Side Scaling") + +class NSGigEPciData(PciConfigData): + VendorID = 0x100B + DeviceID = 0x0022 + Status = 0x0290 + SubClassCode = 0x00 + ClassCode = 0x02 + ProgIF = 0x00 + BAR0 = 0x00000001 + BAR1 = 0x00000000 + BAR2 = 0x00000000 + BAR3 = 0x00000000 + BAR4 = 0x00000000 + BAR5 = 0x00000000 + MaximumLatency = 0x34 + MinimumGrant = 0xb0 + InterruptLine = 0x1e + InterruptPin = 0x01 + BAR0Size = '256B' + BAR1Size = '4kB' + +class NSGigE(EtherDevBase): + type = 'NSGigE' + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + + configdata = NSGigEPciData() + + +class NSGigEInt(EtherInt): + type = 'NSGigEInt' + device = Param.NSGigE("Ethernet device of this interface") + +class SinicPciData(PciConfigData): + VendorID = 0x1291 + DeviceID = 0x1293 + Status = 0x0290 + SubClassCode = 0x00 + ClassCode = 0x02 + ProgIF = 0x00 + BAR0 = 0x00000000 + BAR1 = 0x00000000 + BAR2 = 0x00000000 + BAR3 = 0x00000000 + BAR4 = 0x00000000 + BAR5 = 0x00000000 + MaximumLatency = 0x34 + MinimumGrant = 0xb0 + InterruptLine = 0x1e + InterruptPin = 0x01 + BAR0Size = '64kB' + +class Sinic(EtherDevBase): + type = 'Sinic' + + rx_max_copy = Param.MemorySize('1514B', "rx max copy") + tx_max_copy = Param.MemorySize('16kB', "tx max copy") + rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") + rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") + rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") + tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") + virtual_count = Param.UInt32(1, "Virtualized SINIC") + zero_copy = Param.Bool(False, "Zero copy receive") + delay_copy = Param.Bool(False, "Delayed copy transmit") + virtual_addr = Param.Bool(False, "Virtual addressing") + + configdata = SinicPciData() + +class SinicInt(EtherInt): + type = 'SinicInt' + device = Param.Sinic("Ethernet device of this interface") diff --git a/src/dev/Ide.py b/src/dev/Ide.py new file mode 100644 index 000000000..6bbaad00e --- /dev/null +++ b/src/dev/Ide.py @@ -0,0 +1,68 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from Pci import PciDevice, PciConfigData + +class IdeID(Enum): vals = ['master', 'slave'] + +class IdeControllerPciData(PciConfigData): + VendorID = 0x8086 + DeviceID = 0x7111 + Command = 0x0 + Status = 0x280 + Revision = 0x0 + ClassCode = 0x01 + SubClassCode = 0x01 + ProgIF = 0x85 + BAR0 = 0x00000001 + BAR1 = 0x00000001 + BAR2 = 0x00000001 + BAR3 = 0x00000001 + BAR4 = 0x00000001 + BAR5 = 0x00000001 + InterruptLine = 0x1f + InterruptPin = 0x01 + BAR0Size = '8B' + BAR1Size = '4B' + BAR2Size = '8B' + BAR3Size = '4B' + BAR4Size = '16B' + +class IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Latency('1us', "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + +class IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") + + configdata =IdeControllerPciData() diff --git a/src/dev/Pci.py b/src/dev/Pci.py new file mode 100644 index 000000000..b2c013f41 --- /dev/null +++ b/src/dev/Pci.py @@ -0,0 +1,87 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, DmaDevice, PioDevice + +class PciConfigData(SimObject): + type = 'PciConfigData' + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") + BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") + BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") + BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") + BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") + BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +class PciConfigAll(PioDevice): + type = 'PciConfigAll' + pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + bus = Param.UInt8(0x00, "PCI bus to act as config space for") + size = Param.MemorySize32('16MB', "Size of config space") + + +class PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + config = Port(Self.pio.peerObj.port, "PCI configuration space port") + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") + configdata = Param.PciConfigData(Parent.any, "PCI Config data") + config_latency = Param.Latency('20ns', "Config read or write latency") diff --git a/src/dev/Platform.py b/src/dev/Platform.py new file mode 100644 index 000000000..cb414121b --- /dev/null +++ b/src/dev/Platform.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class Platform(SimObject): + type = 'Platform' + abstract = True + intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/dev/SConscript b/src/dev/SConscript index ea529b536..2e0d75650 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -32,6 +32,17 @@ Import('*') if env['FULL_SYSTEM']: + SimObject('BadDevice.py') + SimObject('Device.py') + SimObject('DiskImage.py') + SimObject('Ethernet.py') + SimObject('Ide.py') + SimObject('Pci.py') + SimObject('Platform.py') + SimObject('SimConsole.py') + SimObject('SimpleDisk.py') + SimObject('Uart.py') + Source('baddev.cc') Source('disk_image.cc') Source('etherbus.cc') diff --git a/src/dev/SimConsole.py b/src/dev/SimConsole.py new file mode 100644 index 000000000..bb8420527 --- /dev/null +++ b/src/dev/SimConsole.py @@ -0,0 +1,39 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class SimConsole(SimObject): + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") + intr_control = Param.IntrControl(Parent.any, "interrupt controller") + port = Param.TcpPort(3456, "listen port") + number = Param.Int(0, "console number") + output = Param.String('console', "file to dump output to") diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py new file mode 100644 index 000000000..1c9193035 --- /dev/null +++ b/src/dev/SimpleDisk.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class SimpleDisk(SimObject): + type = 'SimpleDisk' + disk = Param.DiskImage("Disk Image") + system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/dev/Uart.py b/src/dev/Uart.py new file mode 100644 index 000000000..e32517a4c --- /dev/null +++ b/src/dev/Uart.py @@ -0,0 +1,45 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from m5 import build_env +from Device import BasicPioDevice + +class Uart(BasicPioDevice): + type = 'Uart' + abstract = True + sim_console = Param.SimConsole(Parent.any, "The console") + +class Uart8250(Uart): + type = 'Uart8250' + +if build_env['ALPHA_TLASER']: + class Uart8530(Uart): + type = 'Uart8530' + diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaConsole.py new file mode 100644 index 000000000..43c7ef954 --- /dev/null +++ b/src/dev/alpha/AlphaConsole.py @@ -0,0 +1,38 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice + +class AlphaConsole(BasicPioDevice): + type = 'AlphaConsole' + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") + disk = Param.SimpleDisk("Simple Disk") + sim_console = Param.SimConsole(Parent.any, "The Simulator Console") + system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript index c985fdd9f..8d7f5493b 100644 --- a/src/dev/alpha/SConscript +++ b/src/dev/alpha/SConscript @@ -32,6 +32,9 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha': + SimObject('AlphaConsole.py') + SimObject('Tsunami.py') + Source('console.cc') Source('tsunami.cc') Source('tsunami_cchip.cc') diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py new file mode 100644 index 000000000..484976c09 --- /dev/null +++ b/src/dev/alpha/Tsunami.py @@ -0,0 +1,123 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, IsaFake, BadAddr +from Platform import Platform +from AlphaConsole import AlphaConsole +from Uart import Uart8250 +from Pci import PciConfigAll +from BadDevice import BadDevice + +class TsunamiCChip(BasicPioDevice): + type = 'TsunamiCChip' + tsunami = Param.Tsunami(Parent.any, "Tsunami") + +class TsunamiIO(BasicPioDevice): + type = 'TsunamiIO' + time = Param.Time('01/01/2009', + "System time to use ('Now' for actual time)") + year_is_bcd = Param.Bool(False, + "The RTC should interpret the year as a BCD value") + tsunami = Param.Tsunami(Parent.any, "Tsunami") + frequency = Param.Frequency('1024Hz', "frequency of interrupts") + +class TsunamiPChip(BasicPioDevice): + type = 'TsunamiPChip' + tsunami = Param.Tsunami(Parent.any, "Tsunami") + +class Tsunami(Platform): + type = 'Tsunami' + system = Param.System(Parent.any, "system") + + cchip = TsunamiCChip(pio_addr=0x801a0000000) + pchip = TsunamiPChip(pio_addr=0x80180000000) + pciconfig = PciConfigAll() + fake_sm_chip = IsaFake(pio_addr=0x801fc000370) + + fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) + fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) + fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) + fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) + + fake_ppc = IsaFake(pio_addr=0x801fc0003bb) + + fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) + + fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) + fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) + fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) + fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) + fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) + fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) + fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) + fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) + fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) + fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) + + fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) + fake_ata1 = IsaFake(pio_addr=0x801fc000170) + + fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') + io = TsunamiIO(pio_addr=0x801fc000000) + uart = Uart8250(pio_addr=0x801fc0003f8) + console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIO(self, bus): + self.cchip.pio = bus.port + self.pchip.pio = bus.port + self.pciconfig.pio = bus.default + bus.responder_set = True + bus.responder = self.pciconfig + self.fake_sm_chip.pio = bus.port + self.fake_uart1.pio = bus.port + self.fake_uart2.pio = bus.port + self.fake_uart3.pio = bus.port + self.fake_uart4.pio = bus.port + self.fake_ppc.pio = bus.port + self.fake_OROM.pio = bus.port + self.fake_pnp_addr.pio = bus.port + self.fake_pnp_write.pio = bus.port + self.fake_pnp_read0.pio = bus.port + self.fake_pnp_read1.pio = bus.port + self.fake_pnp_read2.pio = bus.port + self.fake_pnp_read3.pio = bus.port + self.fake_pnp_read4.pio = bus.port + self.fake_pnp_read5.pio = bus.port + self.fake_pnp_read6.pio = bus.port + self.fake_pnp_read7.pio = bus.port + self.fake_ata0.pio = bus.port + self.fake_ata1.pio = bus.port + self.fb.pio = bus.port + self.io.pio = bus.port + self.uart.pio = bus.port + self.console.pio = bus.port diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript index 8511b16fb..2ebf9fe05 100644 --- a/src/dev/sparc/SConscript +++ b/src/dev/sparc/SConscript @@ -32,6 +32,8 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc': + SimObject('T1000.py') + Source('dtod.cc') Source('iob.cc') Source('t1000.cc') diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py new file mode 100644 index 000000000..a033e27e2 --- /dev/null +++ b/src/dev/sparc/T1000.py @@ -0,0 +1,134 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr +from Uart import Uart8250 +from Platform import Platform +from SimConsole import SimConsole + + +class MmDisk(BasicPioDevice): + type = 'MmDisk' + image = Param.DiskImage("Disk Image") + pio_addr = 0x1F40000000 + +class DumbTOD(BasicPioDevice): + type = 'DumbTOD' + time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") + pio_addr = 0xfff0c1fff8 + +class Iob(PioDevice): + type = 'Iob' + pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") + + +class T1000(Platform): + type = 'T1000' + system = Param.System(Parent.any, "system") + + fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) + #warn_access="Accessing Clock Unit -- Unimplemented!") + + fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, + ret_data64=0x0000000000000000, update_data=False) + #warn_access="Accessing Memory Banks -- Unimplemented!") + + fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) + #warn_access="Accessing JBI -- Unimplemented!") + + fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True) + #warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True) + #warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True) + #warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True) + #warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True) + #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True) + #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True) + #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True) + #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) + #warn_access="Accessing SSI -- Unimplemented!") + + hconsole = SimConsole() + hvuart = Uart8250(pio_addr=0xfff0c2c000) + htod = DumbTOD() + + pconsole = SimConsole() + puart0 = Uart8250(pio_addr=0x1f10000000) + + iob = Iob() + # Attach I/O devices that are on chip + def attachOnChipIO(self, bus): + self.iob.pio = bus.port + self.htod.pio = bus.port + + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIO(self, bus): + self.hvuart.sim_console = self.hconsole + self.puart0.sim_console = self.pconsole + self.fake_clk.pio = bus.port + self.fake_membnks.pio = bus.port + self.fake_l2_1.pio = bus.port + self.fake_l2_2.pio = bus.port + self.fake_l2_3.pio = bus.port + self.fake_l2_4.pio = bus.port + self.fake_l2esr_1.pio = bus.port + self.fake_l2esr_2.pio = bus.port + self.fake_l2esr_3.pio = bus.port + self.fake_l2esr_4.pio = bus.port + self.fake_ssi.pio = bus.port + self.fake_jbi.pio = bus.port + self.puart0.pio = bus.port + self.hvuart.pio = bus.port diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py new file mode 100644 index 000000000..8377221cd --- /dev/null +++ b/src/mem/Bridge.py @@ -0,0 +1,44 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.params import * +from MemObject import MemObject + +class Bridge(MemObject): + type = 'Bridge' + side_a = Port('Side A port') + side_b = Port('Side B port') + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") + delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") + write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/mem/Bus.py b/src/mem/Bus.py new file mode 100644 index 000000000..247a1fe31 --- /dev/null +++ b/src/mem/Bus.py @@ -0,0 +1,49 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5 import build_env +from m5.params import * +from m5.proxy import * +from MemObject import MemObject + +if build_env['FULL_SYSTEM']: + from Device import BadAddr + +class Bus(MemObject): + type = 'Bus' + port = VectorPort("vector port for connecting devices") + bus_id = Param.Int(0, "blah") + clock = Param.Clock("1GHz", "bus clock speed") + width = Param.Int(64, "bus width (bytes)") + responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") + if build_env['FULL_SYSTEM']: + responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") + else: + default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py new file mode 100644 index 000000000..269cf4403 --- /dev/null +++ b/src/mem/MemObject.py @@ -0,0 +1,34 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +from m5.SimObject import SimObject +from m5.SimObject import SimObject + +class MemObject(SimObject): + type = 'MemObject' + abstract = True diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py new file mode 100644 index 000000000..2ef3df7c1 --- /dev/null +++ b/src/mem/PhysicalMemory.py @@ -0,0 +1,57 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from MemObject import * + +class PhysicalMemory(MemObject): + type = 'PhysicalMemory' + port = VectorPort("the access port") + range = Param.AddrRange(AddrRange('128MB'), "Device Address") + file = Param.String('', "memory mapped file") + latency = Param.Latency('1t', "latency of an access") + zero = Param.Bool(False, "zero initialize memory") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + diff --git a/src/mem/SConscript b/src/mem/SConscript index 61fb766d6..bbb1e96fe 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -30,6 +30,11 @@ Import('*') +SimObject('Bridge.py') +SimObject('Bus.py') +SimObject('PhysicalMemory.py') +SimObject('MemObject.py') + Source('bridge.cc') Source('bus.cc') Source('dram.cc') diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py new file mode 100644 index 000000000..4b98f6b30 --- /dev/null +++ b/src/mem/cache/BaseCache.py @@ -0,0 +1,91 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from MemObject import MemObject + +class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] + +class BaseCache(MemObject): + type = 'BaseCache' + adaptive_compression = Param.Bool(False, + "Use an adaptive compression scheme") + assoc = Param.Int("associativity") + block_size = Param.Int("block size in bytes") + latency = Param.Latency("Latency") + compressed_bus = Param.Bool(False, + "This cache connects to a compressed memory") + compression_latency = Param.Latency('0ns', + "Latency in cycles of compression algorithm") + hash_delay = Param.Int(1, "time in cycles of hash access") + lifo = Param.Bool(False, + "whether this NIC partition should use LIFO repl. policy") + max_miss_count = Param.Counter(0, + "number of misses to handle before calling exit") + mshrs = Param.Int("number of MSHRs (max outstanding requests)") + prioritizeRequests = Param.Bool(False, + "always service demand misses first") + protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") + repl = Param.Repl(NULL, "replacement policy") + size = Param.MemorySize("capacity in bytes") + split = Param.Bool(False, "whether or not this cache is split") + split_size = Param.Int(0, + "How many ways of the cache belong to CPU/LRU partition") + store_compressed = Param.Bool(False, + "Store compressed data in the cache") + subblock_size = Param.Int(0, + "Size of subblock in IIC used for compression") + tgts_per_mshr = Param.Int("max number of accesses per MSHR") + trace_addr = Param.Addr(0, "address to trace") + two_queue = Param.Bool(False, + "whether the lifo should have two queue replacement") + write_buffers = Param.Int(8, "number of write buffers") + prefetch_miss = Param.Bool(False, + "wheter you are using the hardware prefetcher from Miss stream") + prefetch_access = Param.Bool(False, + "wheter you are using the hardware prefetcher from Access stream") + prefetcher_size = Param.Int(100, + "Number of entries in the harware prefetch queue") + prefetch_past_page = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + prefetch_serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + prefetch_degree = Param.Int(1, + "Degree of the prefetch depth") + prefetch_latency = Param.Tick(10, + "Latency of the prefetcher") + prefetch_policy = Param.Prefetch('none', + "Type of prefetcher to use") + prefetch_cache_check_push = Param.Bool(True, + "Check if in cash on push or pop of prefetch queue") + prefetch_use_cpu_id = Param.Bool(True, + "Use the CPU ID to seperate calculations of prefetches") + prefetch_data_accesses_only = Param.Bool(False, + "Only prefetch on data not on instruction accesses") + cpu_side = Port("Port on side closer to CPU") + mem_side = Port("Port on side closer to MEM") diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 7150719ad..546e037bd 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('BaseCache.py') + Source('base_cache.cc') Source('cache.cc') Source('cache_builder.cc') diff --git a/src/mem/cache/coherence/CoherenceProtocol.py b/src/mem/cache/coherence/CoherenceProtocol.py new file mode 100644 index 000000000..82adb6862 --- /dev/null +++ b/src/mem/cache/coherence/CoherenceProtocol.py @@ -0,0 +1,8 @@ +from m5.SimObject import SimObject +from m5.params import * +class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] + +class CoherenceProtocol(SimObject): + type = 'CoherenceProtocol' + do_upgrades = Param.Bool(True, "use upgrade transactions?") + protocol = Param.Coherence("name of coherence protocol") diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript index 03a2d85d7..4f5966140 100644 --- a/src/mem/cache/coherence/SConscript +++ b/src/mem/cache/coherence/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('CoherenceProtocol.py') + Source('coherence_protocol.cc') Source('uni_coherence.cc') diff --git a/src/mem/cache/tags/Repl.py b/src/mem/cache/tags/Repl.py new file mode 100644 index 000000000..b76aa1d6e --- /dev/null +++ b/src/mem/cache/tags/Repl.py @@ -0,0 +1,11 @@ +from m5.SimObject import SimObject +from m5.params import * +class Repl(SimObject): + type = 'Repl' + abstract = True + +class GenRepl(Repl): + type = 'GenRepl' + fresh_res = Param.Int("Fresh pool residency time") + num_pools = Param.Int("Number of priority pools") + pool_res = Param.Int("Pool residency time") diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index baf71f687..3fcaec4fa 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -38,5 +38,6 @@ Source('split.cc') Source('split_lifo.cc') Source('split_lru.cc') +SimObject('Repl.py') Source('repl/gen.cc') Source('repl/repl.cc') diff --git a/src/python/SConscript b/src/python/SConscript index 562278aa0..66b852d25 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -60,54 +60,3 @@ SwigSource('m5.internal', 'swig/sim_object.i') SwigSource('m5.internal', 'swig/stats.i') SwigSource('m5.internal', 'swig/trace.i') PySource('m5.internal', 'm5/internal/__init__.py') - -SimObject('m5/objects/AlphaConsole.py') -SimObject('m5/objects/AlphaTLB.py') -SimObject('m5/objects/BadDevice.py') -SimObject('m5/objects/BaseCPU.py') -SimObject('m5/objects/BaseCache.py') -SimObject('m5/objects/BaseHier.py') -SimObject('m5/objects/BaseMem.py') -SimObject('m5/objects/BaseMemory.py') -SimObject('m5/objects/BranchPred.py') -SimObject('m5/objects/Bridge.py') -SimObject('m5/objects/Bus.py') -SimObject('m5/objects/Checker.py') -SimObject('m5/objects/CoherenceProtocol.py') -SimObject('m5/objects/DRAMMemory.py') -SimObject('m5/objects/Device.py') -SimObject('m5/objects/DiskImage.py') -SimObject('m5/objects/Ethernet.py') -SimObject('m5/objects/FUPool.py') -SimObject('m5/objects/FastCPU.py') -#SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FuncUnit.py') -SimObject('m5/objects/FuncUnitConfig.py') -SimObject('m5/objects/FunctionalMemory.py') -SimObject('m5/objects/HierParams.py') -SimObject('m5/objects/Ide.py') -SimObject('m5/objects/IntrControl.py') -SimObject('m5/objects/LinuxSystem.py') -SimObject('m5/objects/MainMemory.py') -SimObject('m5/objects/MemObject.py') -SimObject('m5/objects/MemTest.py') -SimObject('m5/objects/MemoryController.py') -SimObject('m5/objects/O3CPU.py') -SimObject('m5/objects/OzoneCPU.py') -SimObject('m5/objects/Pci.py') -SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/Platform.py') -SimObject('m5/objects/Process.py') -SimObject('m5/objects/Repl.py') -SimObject('m5/objects/Root.py') -SimObject('m5/objects/Sampler.py') -SimObject('m5/objects/SimConsole.py') -SimObject('m5/objects/SimpleCPU.py') -SimObject('m5/objects/SimpleDisk.py') -#SimObject('m5/objects/SimpleOzoneCPU.py') -SimObject('m5/objects/SparcTLB.py') -SimObject('m5/objects/System.py') -SimObject('m5/objects/T1000.py') -#SimObject('m5/objects/Tru64System.py') -SimObject('m5/objects/Tsunami.py') -SimObject('m5/objects/Uart.py') diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py deleted file mode 100644 index f968aaa40..000000000 --- a/src/python/m5/objects/AlphaConsole.py +++ /dev/null @@ -1,10 +0,0 @@ -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice - -class AlphaConsole(BasicPioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.cpu[0], "Processor") - disk = Param.SimpleDisk("Simple Disk") - sim_console = Param.SimConsole(Parent.any, "The Simulator Console") - system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py deleted file mode 100644 index af7c04a84..000000000 --- a/src/python/m5/objects/AlphaTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -class AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -class AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py deleted file mode 100644 index 919623887..000000000 --- a/src/python/m5/objects/BadDevice.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.params import * -from Device import BasicPioDevice - -class BadDevice(BasicPioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py deleted file mode 100644 index 986220c3f..000000000 --- a/src/python/m5/objects/BaseCPU.py +++ /dev/null @@ -1,73 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from AlphaTLB import AlphaDTB, AlphaITB -from SparcTLB import SparcDTB, SparcITB -from Bus import Bus -import sys - -class BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - - system = Param.System(Parent.any, "system object") - cpu_id = Param.Int("CPU identifier") - - if build_env['FULL_SYSTEM']: - do_quiesce = Param.Bool(True, "enable quiesce instructions") - do_checkpoint_insts = Param.Bool(True, - "enable checkpoint pseudo instructions") - do_statistics_insts = Param.Bool(True, - "enable statistics pseudo instructions") - - if build_env['TARGET_ISA'] == 'sparc': - dtb = Param.SparcDTB(SparcDTB(), "Data TLB") - itb = Param.SparcITB(SparcITB(), "Instruction TLB") - elif build_env['TARGET_ISA'] == 'alpha': - dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") - itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") - else: - print "Unknown architecture, can't pick TLBs" - sys.exit(1) - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - progress_interval = Param.Tick(0, - "interval to print out the progress message") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") - - clock = Param.Clock('1t', "clock speed") - phase = Param.Latency('0ns', "clock phase") - - _mem_ports = [] - - def connectMemPorts(self, bus): - for p in self._mem_ports: - exec('self.%s = bus.port' % p) - - def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2) - self.icache = ic - self.dcache = dc - self.icache_port = ic.cpu_side - self.dcache_port = dc.cpu_side - self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] - - def addTwoLevelCacheHierarchy(self, ic, dc, l2c): - self.addPrivateSplitL1Caches(ic, dc) - self.toL2Bus = Bus() - self.connectMemPorts(self.toL2Bus) - self.l2cache = l2c - self.l2cache.cpu_side = self.toL2Bus.port - self._mem_ports = ['l2cache.mem_side'] diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py deleted file mode 100644 index 7df5215e4..000000000 --- a/src/python/m5/objects/BaseCache.py +++ /dev/null @@ -1,63 +0,0 @@ -from m5.params import * -from MemObject import MemObject - -class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] - -class BaseCache(MemObject): - type = 'BaseCache' - adaptive_compression = Param.Bool(False, - "Use an adaptive compression scheme") - assoc = Param.Int("associativity") - block_size = Param.Int("block size in bytes") - latency = Param.Latency("Latency") - compressed_bus = Param.Bool(False, - "This cache connects to a compressed memory") - compression_latency = Param.Latency('0ns', - "Latency in cycles of compression algorithm") - hash_delay = Param.Int(1, "time in cycles of hash access") - lifo = Param.Bool(False, - "whether this NIC partition should use LIFO repl. policy") - max_miss_count = Param.Counter(0, - "number of misses to handle before calling exit") - mshrs = Param.Int("number of MSHRs (max outstanding requests)") - prioritizeRequests = Param.Bool(False, - "always service demand misses first") - protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") - repl = Param.Repl(NULL, "replacement policy") - size = Param.MemorySize("capacity in bytes") - split = Param.Bool(False, "whether or not this cache is split") - split_size = Param.Int(0, - "How many ways of the cache belong to CPU/LRU partition") - store_compressed = Param.Bool(False, - "Store compressed data in the cache") - subblock_size = Param.Int(0, - "Size of subblock in IIC used for compression") - tgts_per_mshr = Param.Int("max number of accesses per MSHR") - trace_addr = Param.Addr(0, "address to trace") - two_queue = Param.Bool(False, - "whether the lifo should have two queue replacement") - write_buffers = Param.Int(8, "number of write buffers") - prefetch_miss = Param.Bool(False, - "wheter you are using the hardware prefetcher from Miss stream") - prefetch_access = Param.Bool(False, - "wheter you are using the hardware prefetcher from Access stream") - prefetcher_size = Param.Int(100, - "Number of entries in the harware prefetch queue") - prefetch_past_page = Param.Bool(False, - "Allow prefetches to cross virtual page boundaries") - prefetch_serial_squash = Param.Bool(False, - "Squash prefetches with a later time on a subsequent miss") - prefetch_degree = Param.Int(1, - "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, - "Latency of the prefetcher") - prefetch_policy = Param.Prefetch('none', - "Type of prefetcher to use") - prefetch_cache_check_push = Param.Bool(True, - "Check if in cash on push or pop of prefetch queue") - prefetch_use_cpu_id = Param.Bool(True, - "Use the CPU ID to seperate calculations of prefetches") - prefetch_data_accesses_only = Param.Bool(False, - "Only prefetch on data not on instruction accesses") - cpu_side = Port("Port on side closer to CPU") - mem_side = Port("Port on side closer to MEM") diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py deleted file mode 100644 index 33b24ad3c..000000000 --- a/src/python/m5/objects/Bridge.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.params import * -from MemObject import MemObject - -class Bridge(MemObject): - type = 'Bridge' - side_a = Port('Side A port') - side_b = Port('Side B port') - req_size_a = Param.Int(16, "The number of requests to buffer") - req_size_b = Param.Int(16, "The number of requests to buffer") - resp_size_a = Param.Int(16, "The number of requests to buffer") - resp_size_b = Param.Int(16, "The number of requests to buffer") - delay = Param.Latency('0ns', "The latency of this bridge") - nack_delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") - fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") - fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py deleted file mode 100644 index 48dbbe307..000000000 --- a/src/python/m5/objects/Bus.py +++ /dev/null @@ -1,19 +0,0 @@ -from m5 import build_env -from m5.params import * -from m5.proxy import * -from MemObject import MemObject -from Device import BadAddr - -class Bus(MemObject): - type = 'Bus' - port = VectorPort("vector port for connecting devices") - bus_id = Param.Int(0, "blah") - clock = Param.Clock("1GHz", "bus clock speed") - width = Param.Int(64, "bus width (bytes)") - responder_set = Param.Bool(False, "Did the user specify a default responder.") - block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") - if build_env['FULL_SYSTEM']: - responder = BadAddr(pio_addr=0x0, pio_latency="1ps") - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") - else: - default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py deleted file mode 100644 index 82adb6862..000000000 --- a/src/python/m5/objects/CoherenceProtocol.py +++ /dev/null @@ -1,8 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] - -class CoherenceProtocol(SimObject): - type = 'CoherenceProtocol' - do_upgrades = Param.Bool(True, "use upgrade transactions?") - protocol = Param.Coherence("name of coherence protocol") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py deleted file mode 100644 index 90fbfb552..000000000 --- a/src/python/m5/objects/Device.py +++ /dev/null @@ -1,43 +0,0 @@ -from m5.params import * -from m5.proxy import * -from MemObject import MemObject - -class PioDevice(MemObject): - type = 'PioDevice' - abstract = True - pio = Port("Programmed I/O port") - platform = Param.Platform(Parent.any, "Platform this device is part of") - system = Param.System(Parent.any, "System this device is part of") - -class BasicPioDevice(PioDevice): - type = 'BasicPioDevice' - abstract = True - pio_addr = Param.Addr("Device Address") - pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") - -class DmaDevice(PioDevice): - type = 'DmaDevice' - abstract = True - dma = Port(Self.pio.peerObj.port, "DMA port") - min_backoff_delay = Param.Latency('4ns', - "min time between a nack packet being received and the next request made by the device") - max_backoff_delay = Param.Latency('10us', - "max time between a nack packet being received and the next request made by the device") - - - -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data8 = Param.UInt8(0xFF, "Default data to return") - ret_data16 = Param.UInt16(0xFFFF, "Default data to return") - ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") - ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - update_data = Param.Bool(False, "Update the data that is returned on writes") - warn_access = Param.String("", "String to print when device is accessed") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - - diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py deleted file mode 100644 index d0ada7ee1..000000000 --- a/src/python/m5/objects/DiskImage.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -class RawDiskImage(DiskImage): - type = 'RawDiskImage' - -class CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage(RawDiskImage(read_only=True), - "child image") - table_size = Param.Int(65536, "initial table size") diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py deleted file mode 100644 index bfe30950c..000000000 --- a/src/python/m5/objects/Ethernet.py +++ /dev/null @@ -1,200 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from Device import DmaDevice -from Pci import PciDevice, PciConfigData - -class EtherInt(SimObject): - type = 'EtherInt' - abstract = True - peer = Param.EtherInt(NULL, "peer interface") - -class EtherLink(SimObject): - type = 'EtherLink' - int1 = Param.EtherInt("interface 1") - int2 = Param.EtherInt("interface 2") - delay = Param.Latency('0us', "packet transmit delay") - delay_var = Param.Latency('0ns', "packet transmit delay variability") - speed = Param.NetworkBandwidth('1Gbps', "link speed") - dump = Param.EtherDump(NULL, "dump object") - -class EtherBus(SimObject): - type = 'EtherBus' - loopback = Param.Bool(True, "send packet back to the sending interface") - dump = Param.EtherDump(NULL, "dump object") - speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") - -class EtherTap(EtherInt): - type = 'EtherTap' - bufsz = Param.Int(10000, "tap buffer size") - dump = Param.EtherDump(NULL, "dump object") - port = Param.UInt16(3500, "tap port") - -class EtherDump(SimObject): - type = 'EtherDump' - file = Param.String("dump file") - maxlen = Param.Int(96, "max portion of packet data to dump") - -if build_env['ALPHA_TLASER']: - - class EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - tlaser = Param.Turbolaser(Parent.any, "Turbolaser") - - class EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - - -class IGbE(PciDevice): - type = 'IGbE' - hardware_address = Param.String("Ethernet Hardware Address") - use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)") - rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") - tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") - rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") - tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") - clock = Param.Clock('500MHz', "Clock speed of the device") - - -class IGbEPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x1075 - SubsystemID = 0x1008 - SubsystemVendorID = 0x8086 - Status = 0x0000 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000000 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x00 - MinimumGrant = 0xff - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '128kB' - -class IGbEInt(EtherInt): - type = 'IGbEInt' - device = Param.IGbE("Ethernet device of this interface") - - - -class EtherDevBase(PciDevice): - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - clock = Param.Clock('0ns', "State machine processor frequency") - - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") - tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - intr_delay = Param.Latency('10us', "Interrupt propagation delay") - rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") - tx_thread = Param.Bool(False, "dedicated kernel threads for receive") - rss = Param.Bool(False, "Receive Side Scaling") - -class NSGigEPciData(PciConfigData): - VendorID = 0x100B - DeviceID = 0x0022 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000001 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '256B' - BAR1Size = '4kB' - -class NSGigE(EtherDevBase): - type = 'NSGigE' - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - configdata = NSGigEPciData() - - -class NSGigEInt(EtherInt): - type = 'NSGigEInt' - device = Param.NSGigE("Ethernet device of this interface") - -class SinicPciData(PciConfigData): - VendorID = 0x1291 - DeviceID = 0x1293 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000000 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '64kB' - -class Sinic(EtherDevBase): - type = 'Sinic' - - rx_max_copy = Param.MemorySize('1514B', "rx max copy") - tx_max_copy = Param.MemorySize('16kB', "tx max copy") - rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") - rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") - rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") - tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") - tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") - virtual_count = Param.UInt32(1, "Virtualized SINIC") - zero_copy = Param.Bool(False, "Zero copy receive") - delay_copy = Param.Bool(False, "Delayed copy transmit") - virtual_addr = Param.Bool(False, "Virtual addressing") - - configdata = SinicPciData() - -class SinicInt(EtherInt): - type = 'SinicInt' - device = Param.Sinic("Ethernet device of this interface") diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py deleted file mode 100644 index 916183bd7..000000000 --- a/src/python/m5/objects/FUPool.py +++ /dev/null @@ -1,12 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * -from FuncUnitConfig import * - -class FUPool(SimObject): - type = 'FUPool' - FUList = VectorParam.FUDesc("list of FU's for this pool") - -class DefaultFUPool(FUPool): - FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - WritePort(), RdWrPort(), IprPort() ] diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py deleted file mode 100644 index f0ad55f7a..000000000 --- a/src/python/m5/objects/FuncUnit.py +++ /dev/null @@ -1,18 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class OpType(Enum): - vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', - 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', - 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] - -class OpDesc(SimObject): - type = 'OpDesc' - issueLat = Param.Int(1, "cycles until another can be issued") - opClass = Param.OpType("type of operation") - opLat = Param.Int(1, "cycles until result is available") - -class FUDesc(SimObject): - type = 'FUDesc' - count = Param.Int("number of these FU's available") - opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py deleted file mode 100644 index 43d7a4bb7..000000000 --- a/src/python/m5/objects/FuncUnitConfig.py +++ /dev/null @@ -1,41 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * - -class IntALU(FUDesc): - opList = [ OpDesc(opClass='IntAlu') ] - count = 6 - -class IntMultDiv(FUDesc): - opList = [ OpDesc(opClass='IntMult', opLat=3), - OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] - count=2 - -class FP_ALU(FUDesc): - opList = [ OpDesc(opClass='FloatAdd', opLat=2), - OpDesc(opClass='FloatCmp', opLat=2), - OpDesc(opClass='FloatCvt', opLat=2) ] - count = 4 - -class FP_MultDiv(FUDesc): - opList = [ OpDesc(opClass='FloatMult', opLat=4), - OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), - OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] - count = 2 - -class ReadPort(FUDesc): - opList = [ OpDesc(opClass='MemRead') ] - count = 0 - -class WritePort(FUDesc): - opList = [ OpDesc(opClass='MemWrite') ] - count = 0 - -class RdWrPort(FUDesc): - opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] - count = 4 - -class IprPort(FUDesc): - opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] - count = 1 - diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py deleted file mode 100644 index ef7e28785..000000000 --- a/src/python/m5/objects/Ide.py +++ /dev/null @@ -1,40 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from Pci import PciDevice, PciConfigData - -class IdeID(Enum): vals = ['master', 'slave'] - -class IdeControllerPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x7111 - Command = 0x0 - Status = 0x280 - Revision = 0x0 - ClassCode = 0x01 - SubClassCode = 0x01 - ProgIF = 0x85 - BAR0 = 0x00000001 - BAR1 = 0x00000001 - BAR2 = 0x00000001 - BAR3 = 0x00000001 - BAR4 = 0x00000001 - BAR5 = 0x00000001 - InterruptLine = 0x1f - InterruptPin = 0x01 - BAR0Size = '8B' - BAR1Size = '4B' - BAR2Size = '8B' - BAR3Size = '4B' - BAR4Size = '16B' - -class IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - -class IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") - - configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py deleted file mode 100644 index 398ba47f9..000000000 --- a/src/python/m5/objects/IntrControl.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class IntrControl(SimObject): - type = 'IntrControl' - sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py deleted file mode 100644 index 8982d553d..000000000 --- a/src/python/m5/objects/MemObject.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.SimObject import SimObject - -class MemObject(SimObject): - type = 'MemObject' - abstract = True diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py deleted file mode 100644 index 1219ddd4d..000000000 --- a/src/python/m5/objects/MemTest.py +++ /dev/null @@ -1,24 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env - -class MemTest(SimObject): - type = 'MemTest' - max_loads = Param.Counter("number of loads to execute") - atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") - memory_size = Param.Int(65536, "memory size") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_functional = Param.Percent(50, "percent of access that are functional") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") - - test = Port("Port to the memory system to test") - functional = Port("Port to the functional memory used for verification") diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py deleted file mode 100644 index 5fba4e96f..000000000 --- a/src/python/m5/objects/O3CPU.py +++ /dev/null @@ -1,123 +0,0 @@ -from m5.params import * -from m5.proxy import * -from m5 import build_env -from BaseCPU import BaseCPU -from Checker import O3Checker -from FUPool import * - -class DerivO3CPU(BaseCPU): - type = 'DerivO3CPU' - activity = Param.Unsigned(0, "Initial count") - numThreads = Param.Unsigned(1, "number of HW thread contexts") - - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") - if build_env['USE_CHECKER']: - if not build_env['FULL_SYSTEM']: - checker = Param.BaseCPU(O3Checker(workload=Parent.workload, - exitOnError=False, - updateOnError=True, - warnOnlyOnLoadError=False), - "checker") - else: - checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, - warnOnlyOnLoadError=False), "checker") - checker.itb = Parent.itb - checker.dtb = Parent.dtb - - cachePorts = Param.Unsigned("Cache Ports") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] - - decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") - renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") - iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") - fetchWidth = Param.Unsigned(8, "Fetch width") - - renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") - iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") - decodeWidth = Param.Unsigned(8, "Decode width") - - iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") - decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") - renameWidth = Param.Unsigned(8, "Rename width") - - commitToIEWDelay = Param.Unsigned(1, "Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned(2, "Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " - "to the IEW stage)") - dispatchWidth = Param.Unsigned(8, "Dispatch width") - issueWidth = Param.Unsigned(8, "Issue width") - wbWidth = Param.Unsigned(8, "Writeback width") - wbDepth = Param.Unsigned(1, "Writeback depth") - fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") - - iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") - commitWidth = Param.Unsigned(8, "Commit width") - squashWidth = Param.Unsigned(8, "Squash width") - trapLatency = Param.Tick(13, "Trap latency") - fetchTrapLatency = Param.Tick(1, "Fetch trap latency") - - backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") - forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") - - predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") - localPredictorSize = Param.Unsigned(2048, "Size of local predictor") - localCtrBits = Param.Unsigned(2, "Bits per counter") - localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") - localHistoryBits = Param.Unsigned(11, "Bits for the local history") - globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") - globalCtrBits = Param.Unsigned(2, "Bits per counter") - globalHistoryBits = Param.Unsigned(13, "Bits of history") - choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") - choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") - - BTBEntries = Param.Unsigned(4096, "Number of BTB entries") - BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") - - RASSize = Param.Unsigned(16, "RAS size") - - LQEntries = Param.Unsigned(32, "Number of load queue entries") - SQEntries = Param.Unsigned(32, "Number of store queue entries") - LFSTSize = Param.Unsigned(1024, "Last fetched store table size") - SSITSize = Param.Unsigned(1024, "Store set ID table size") - - numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); - - numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") - numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") - - smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") - smtFetchPolicy = Param.String("SMT Fetch policy") - smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") - smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") - smtIQPolicy = Param.String("SMT IQ Sharing Policy") - smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") - smtROBPolicy = Param.String("SMT ROB Sharing Policy") - smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") - smtCommitPolicy = Param.String("SMT Commit Policy") - - def addPrivateSplitL1Caches(self, ic, dc): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc) - self.icache.tgts_per_mshr = 20 - self.dcache.tgts_per_mshr = 20 diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py deleted file mode 100644 index 0913e044c..000000000 --- a/src/python/m5/objects/OzoneCPU.py +++ /dev/null @@ -1,95 +0,0 @@ -from m5.params import * -from m5 import build_env -from BaseCPU import BaseCPU - -class DerivOzoneCPU(BaseCPU): - type = 'DerivOzoneCPU' - - numThreads = Param.Unsigned("number of HW thread contexts") - - checker = Param.BaseCPU("Checker CPU") - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") - - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - - width = Param.Unsigned("Width") - frontEndWidth = Param.Unsigned("Front end width") - frontEndLatency = Param.Unsigned("Front end latency") - backEndWidth = Param.Unsigned("Back end width") - backEndSquashLatency = Param.Unsigned("Back end squash latency") - backEndLatency = Param.Unsigned("Back end latency") - maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size") - maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations") - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - - predType = Param.String("Type of branch predictor ('local', 'tournament')") - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - lsqLimits = Param.Bool(True, "LSQ size limits dispatch") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py deleted file mode 100644 index 9d40adbfe..000000000 --- a/src/python/m5/objects/Pci.py +++ /dev/null @@ -1,59 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice, DmaDevice, PioDevice - -class PciConfigData(SimObject): - type = 'PciConfigData' - VendorID = Param.UInt16("Vendor ID") - DeviceID = Param.UInt16("Device ID") - Command = Param.UInt16(0, "Command") - Status = Param.UInt16(0, "Status") - Revision = Param.UInt8(0, "Device") - ProgIF = Param.UInt8(0, "Programming Interface") - SubClassCode = Param.UInt8(0, "Sub-Class Code") - ClassCode = Param.UInt8(0, "Class Code") - CacheLineSize = Param.UInt8(0, "System Cacheline Size") - LatencyTimer = Param.UInt8(0, "PCI Latency Timer") - HeaderType = Param.UInt8(0, "PCI Header Type") - BIST = Param.UInt8(0, "Built In Self Test") - - BAR0 = Param.UInt32(0x00, "Base Address Register 0") - BAR1 = Param.UInt32(0x00, "Base Address Register 1") - BAR2 = Param.UInt32(0x00, "Base Address Register 2") - BAR3 = Param.UInt32(0x00, "Base Address Register 3") - BAR4 = Param.UInt32(0x00, "Base Address Register 4") - BAR5 = Param.UInt32(0x00, "Base Address Register 5") - BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") - BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") - BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") - BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") - BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") - BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") - - CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") - SubsystemID = Param.UInt16(0x00, "Subsystem ID") - SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") - ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") - InterruptLine = Param.UInt8(0x00, "Interrupt Line") - InterruptPin = Param.UInt8(0x00, "Interrupt Pin") - MaximumLatency = Param.UInt8(0x00, "Maximum Latency") - MinimumGrant = Param.UInt8(0x00, "Minimum Grant") - -class PciConfigAll(PioDevice): - type = 'PciConfigAll' - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") - bus = Param.UInt8(0x00, "PCI bus to act as config space for") - size = Param.MemorySize32('16MB', "Size of config space") - - -class PciDevice(DmaDevice): - type = 'PciDevice' - abstract = True - config = Port(Self.pio.peerObj.port, "PCI configuration space port") - pci_bus = Param.Int("PCI bus") - pci_dev = Param.Int("PCI device number") - pci_func = Param.Int("PCI function code") - pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") - configdata = Param.PciConfigData(Parent.any, "PCI Config data") - config_latency = Param.Latency('20ns', "Config read or write latency") diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py deleted file mode 100644 index 83dbc7710..000000000 --- a/src/python/m5/objects/PhysicalMemory.py +++ /dev/null @@ -1,29 +0,0 @@ -from m5.params import * -from m5.proxy import * -from MemObject import * - -class PhysicalMemory(MemObject): - type = 'PhysicalMemory' - port = VectorPort("the access port") - range = Param.AddrRange(AddrRange('128MB'), "Device Address") - file = Param.String('', "memory mapped file") - latency = Param.Latency('1t', "latency of an access") - zero = Param.Bool(False, "zero initialize memory") - -class DRAMMemory(PhysicalMemory): - type = 'DRAMMemory' - # Many of these should be observed from the configuration - cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") - mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") - mem_actpolicy = Param.String("open", "Open/Close policy") - memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") - bus_width = Param.Int(16, "") - act_lat = Param.Int(2, "RAS to CAS delay") - cas_lat = Param.Int(1, "CAS delay") - war_lat = Param.Int(2, "write after read delay") - pre_lat = Param.Int(2, "precharge delay") - dpl_lat = Param.Int(2, "data in to precharge delay") - trc_lat = Param.Int(6, "row cycle delay") - num_banks = Param.Int(4, "Number of Banks") - num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") - diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py deleted file mode 100644 index ab2083eea..000000000 --- a/src/python/m5/objects/Platform.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Platform(SimObject): - type = 'Platform' - abstract = True - intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py deleted file mode 100644 index 79268e6f4..000000000 --- a/src/python/m5/objects/Process.py +++ /dev/null @@ -1,36 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - system = Param.System(Parent.any, "system process will run on") - -class LiveProcess(Process): - type = 'LiveProcess' - executable = Param.String('', "executable (overrides cmd[0] if set)") - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - cwd = Param.String('', "current working directory") - input = Param.String('cin', "filename for stdin") - uid = Param.Int(100, 'user id') - euid = Param.Int(100, 'effective user id') - gid = Param.Int(100, 'group id') - egid = Param.Int(100, 'effective group id') - pid = Param.Int(100, 'process id') - ppid = Param.Int(99, 'parent process id') - -class AlphaLiveProcess(LiveProcess): - type = 'AlphaLiveProcess' - -class SparcLiveProcess(LiveProcess): - type = 'SparcLiveProcess' - -class MipsLiveProcess(LiveProcess): - type = 'MipsLiveProcess' - -class EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py deleted file mode 100644 index b76aa1d6e..000000000 --- a/src/python/m5/objects/Repl.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class Repl(SimObject): - type = 'Repl' - abstract = True - -class GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("Fresh pool residency time") - num_pools = Param.Int("Number of priority pools") - pool_res = Param.Int("Pool residency time") diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py deleted file mode 100644 index 2b0e736e7..000000000 --- a/src/python/m5/objects/Root.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class Root(SimObject): - type = 'Root' - dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py deleted file mode 100644 index dfad18eb6..000000000 --- a/src/python/m5/objects/SimConsole.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * - -class SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Parent.any, "interrupt controller") - port = Param.TcpPort(3456, "listen port") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py deleted file mode 100644 index 099a77dbb..000000000 --- a/src/python/m5/objects/SimpleDisk.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py deleted file mode 100644 index 193f31b0f..000000000 --- a/src/python/m5/objects/SimpleOzoneCPU.py +++ /dev/null @@ -1,87 +0,0 @@ -from m5.params import * -from m5 import build_env -from BaseCPU import BaseCPU - -class SimpleOzoneCPU(BaseCPU): - type = 'SimpleOzoneCPU' - - numThreads = Param.Unsigned("number of HW thread contexts") - - if not build_env['FULL_SYSTEM']: - mem = Param.FunctionalMemory(NULL, "memory") - - width = Param.Unsigned("Width") - frontEndWidth = Param.Unsigned("Front end width") - backEndWidth = Param.Unsigned("Back end width") - backEndSquashLatency = Param.Unsigned("Back end squash latency") - backEndLatency = Param.Unsigned("Back end latency") - maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size") - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py deleted file mode 100644 index 06d2a8231..000000000 --- a/src/python/m5/objects/SparcTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class SparcTLB(SimObject): - type = 'SparcTLB' - abstract = True - size = Param.Int("TLB size") - -class SparcDTB(SparcTLB): - type = 'SparcDTB' - size = 64 - -class SparcITB(SparcTLB): - type = 'SparcITB' - size = 64 diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py deleted file mode 100644 index 810a320be..000000000 --- a/src/python/m5/objects/System.py +++ /dev/null @@ -1,68 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from PhysicalMemory import * - -class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] - -class System(SimObject): - type = 'System' - physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") - mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") - if build_env['FULL_SYSTEM']: - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, - "boot processor frequency") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("", "file that contains the kernel code") - readfile = Param.String("", "file to read startup script from") - symbolfile = Param.String("", "file to get the symbols from") - -class AlphaSystem(System): - type = 'AlphaSystem' - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - -class SparcSystem(System): - type = 'SparcSystem' - _rom_base = 0xfff0000000 - _nvram_base = 0x1f11000000 - _hypervisor_desc_base = 0x1f12080000 - _partition_desc_base = 0x1f12000000 - # ROM for OBP/Reset/Hypervisor - rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')), - "Memory to hold the ROM data") - # nvram - nvram = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')), - "Memory to hold the nvram data") - # hypervisor description - hypervisor_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')), - "Memory to hold the hypervisor description") - # partition description - partition_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')), - "Memory to hold the partition description") - - reset_addr = Param.Addr(_rom_base, "Address to load ROM at") - hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, - "Address to load hypervisor at") - openboot_addr = Param.Addr(Addr('512kB') + _rom_base, - "Address to load openboot at") - nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") - hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, - "Address for the hypervisor description") - partition_desc_addr = Param.Addr(_partition_desc_base, - "Address for the partition description") - - reset_bin = Param.String("file that contains the reset code") - hypervisor_bin = Param.String("file that contains the hypervisor code") - openboot_bin = Param.String("file that contains the openboot code") - nvram_bin = Param.String("file that contains the contents of nvram") - hypervisor_desc_bin = Param.String("file that contains the hypervisor description") - partition_desc_bin = Param.String("file that contains the partition description") - diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py deleted file mode 100644 index 0acfa0920..000000000 --- a/src/python/m5/objects/T1000.py +++ /dev/null @@ -1,106 +0,0 @@ -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr -from Uart import Uart8250 -from Platform import Platform -from SimConsole import SimConsole - - -class MmDisk(BasicPioDevice): - type = 'MmDisk' - image = Param.DiskImage("Disk Image") - pio_addr = 0x1F40000000 - -class DumbTOD(BasicPioDevice): - type = 'DumbTOD' - time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") - pio_addr = 0xfff0c1fff8 - -class Iob(PioDevice): - type = 'Iob' - pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") - - -class T1000(Platform): - type = 'T1000' - system = Param.System(Parent.any, "system") - - fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) - #warn_access="Accessing Clock Unit -- Unimplemented!") - - fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, - ret_data64=0x0000000000000000, update_data=False) - #warn_access="Accessing Memory Banks -- Unimplemented!") - - fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) - #warn_access="Accessing JBI -- Unimplemented!") - - fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, - ret_data64=0x0000000000000001, update_data=True) - #warn_access="Accessing L2 Cache Banks -- Unimplemented!") - - fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, - ret_data64=0x0000000000000001, update_data=True) - #warn_access="Accessing L2 Cache Banks -- Unimplemented!") - - fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, - ret_data64=0x0000000000000001, update_data=True) - #warn_access="Accessing L2 Cache Banks -- Unimplemented!") - - fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, - ret_data64=0x0000000000000001, update_data=True) - #warn_access="Accessing L2 Cache Banks -- Unimplemented!") - - fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, - ret_data64=0x0000000000000000, update_data=True) - #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") - - fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, - ret_data64=0x0000000000000000, update_data=True) - #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") - - fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, - ret_data64=0x0000000000000000, update_data=True) - #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") - - fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, - ret_data64=0x0000000000000000, update_data=True) - #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") - - fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) - #warn_access="Accessing SSI -- Unimplemented!") - - hconsole = SimConsole() - hvuart = Uart8250(pio_addr=0xfff0c2c000) - htod = DumbTOD() - - pconsole = SimConsole() - puart0 = Uart8250(pio_addr=0x1f10000000) - - iob = Iob() - # Attach I/O devices that are on chip - def attachOnChipIO(self, bus): - self.iob.pio = bus.port - self.htod.pio = bus.port - - - # Attach I/O devices to specified bus object. Can't do this - # earlier, since the bus object itself is typically defined at the - # System level. - def attachIO(self, bus): - self.hvuart.sim_console = self.hconsole - self.puart0.sim_console = self.pconsole - self.fake_clk.pio = bus.port - self.fake_membnks.pio = bus.port - self.fake_l2_1.pio = bus.port - self.fake_l2_2.pio = bus.port - self.fake_l2_3.pio = bus.port - self.fake_l2_4.pio = bus.port - self.fake_l2esr_1.pio = bus.port - self.fake_l2esr_2.pio = bus.port - self.fake_l2esr_3.pio = bus.port - self.fake_l2esr_4.pio = bus.port - self.fake_ssi.pio = bus.port - self.fake_jbi.pio = bus.port - self.puart0.pio = bus.port - self.hvuart.pio = bus.port diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py deleted file mode 100644 index 85105ff20..000000000 --- a/src/python/m5/objects/Tsunami.py +++ /dev/null @@ -1,95 +0,0 @@ -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice, IsaFake, BadAddr -from Platform import Platform -from AlphaConsole import AlphaConsole -from Uart import Uart8250 -from Pci import PciConfigAll -from BadDevice import BadDevice - -class TsunamiCChip(BasicPioDevice): - type = 'TsunamiCChip' - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class TsunamiIO(BasicPioDevice): - type = 'TsunamiIO' - time = Param.Time('01/01/2009', - "System time to use ('Now' for actual time)") - year_is_bcd = Param.Bool(False, - "The RTC should interpret the year as a BCD value") - tsunami = Param.Tsunami(Parent.any, "Tsunami") - frequency = Param.Frequency('1024Hz', "frequency of interrupts") - -class TsunamiPChip(BasicPioDevice): - type = 'TsunamiPChip' - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class Tsunami(Platform): - type = 'Tsunami' - system = Param.System(Parent.any, "system") - - cchip = TsunamiCChip(pio_addr=0x801a0000000) - pchip = TsunamiPChip(pio_addr=0x80180000000) - pciconfig = PciConfigAll() - fake_sm_chip = IsaFake(pio_addr=0x801fc000370) - - fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) - fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) - fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) - fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) - - fake_ppc = IsaFake(pio_addr=0x801fc0003bb) - - fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) - - fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) - fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) - fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) - fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) - fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) - fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) - fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) - fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) - fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) - fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) - - fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) - fake_ata1 = IsaFake(pio_addr=0x801fc000170) - - fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') - io = TsunamiIO(pio_addr=0x801fc000000) - uart = Uart8250(pio_addr=0x801fc0003f8) - console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) - - # Attach I/O devices to specified bus object. Can't do this - # earlier, since the bus object itself is typically defined at the - # System level. - def attachIO(self, bus): - self.cchip.pio = bus.port - self.pchip.pio = bus.port - self.pciconfig.pio = bus.default - bus.responder_set = True - bus.responder = self.pciconfig - self.fake_sm_chip.pio = bus.port - self.fake_uart1.pio = bus.port - self.fake_uart2.pio = bus.port - self.fake_uart3.pio = bus.port - self.fake_uart4.pio = bus.port - self.fake_ppc.pio = bus.port - self.fake_OROM.pio = bus.port - self.fake_pnp_addr.pio = bus.port - self.fake_pnp_write.pio = bus.port - self.fake_pnp_read0.pio = bus.port - self.fake_pnp_read1.pio = bus.port - self.fake_pnp_read2.pio = bus.port - self.fake_pnp_read3.pio = bus.port - self.fake_pnp_read4.pio = bus.port - self.fake_pnp_read5.pio = bus.port - self.fake_pnp_read6.pio = bus.port - self.fake_pnp_read7.pio = bus.port - self.fake_ata0.pio = bus.port - self.fake_ata1.pio = bus.port - self.fb.pio = bus.port - self.io.pio = bus.port - self.uart.pio = bus.port - self.console.pio = bus.port diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py deleted file mode 100644 index 62062c6b1..000000000 --- a/src/python/m5/objects/Uart.py +++ /dev/null @@ -1,17 +0,0 @@ -from m5.params import * -from m5.proxy import * -from m5 import build_env -from Device import BasicPioDevice - -class Uart(BasicPioDevice): - type = 'Uart' - abstract = True - sim_console = Param.SimConsole(Parent.any, "The console") - -class Uart8250(Uart): - type = 'Uart8250' - -if build_env['ALPHA_TLASER']: - class Uart8530(Uart): - type = 'Uart8530' - diff --git a/src/sim/Process.py b/src/sim/Process.py new file mode 100644 index 000000000..16be65fd4 --- /dev/null +++ b/src/sim/Process.py @@ -0,0 +1,51 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class Process(SimObject): + type = 'Process' + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + system = Param.System(Parent.any, "system process will run on") + +class LiveProcess(Process): + type = 'LiveProcess' + executable = Param.String('', "executable (overrides cmd[0] if set)") + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + cwd = Param.String('', "current working directory") + input = Param.String('cin', "filename for stdin") + uid = Param.Int(100, 'user id') + euid = Param.Int(100, 'effective user id') + gid = Param.Int(100, 'group id') + egid = Param.Int(100, 'effective group id') + pid = Param.Int(100, 'process id') + ppid = Param.Int(99, 'parent process id') diff --git a/src/sim/Root.py b/src/sim/Root.py new file mode 100644 index 000000000..fff998e0d --- /dev/null +++ b/src/sim/Root.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * + +class Root(SimObject): + type = 'Root' + dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/sim/SConscript b/src/sim/SConscript index 46dc2c8dd..50f966bcf 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,6 +30,9 @@ Import('*') +SimObject('Root.py') +SimObject('System.py') + Source('async.cc') Source('builder.cc') Source('core.cc') @@ -50,5 +53,7 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('pseudo_inst.cc') else: + SimObject('Process.py') + Source('process.cc') Source('syscall_emul.cc') diff --git a/src/sim/System.py b/src/sim/System.py new file mode 100644 index 000000000..b37e385c1 --- /dev/null +++ b/src/sim/System.py @@ -0,0 +1,48 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env +from PhysicalMemory import * + +class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] + +class System(SimObject): + type = 'System' + physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") + mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") + if build_env['FULL_SYSTEM']: + boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, + "boot processor frequency") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + kernel = Param.String("", "file that contains the kernel code") + readfile = Param.String("", "file to read startup script from") + symbolfile = Param.String("", "file to get the symbols from") -- cgit v1.2.3 From 07bda077f27c10e227373914a7515e43c6f0a578 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 28 May 2007 08:03:13 -0700 Subject: Remove unnecessary include of physical.hh. --HG-- extra : convert_revision : bccafe884e58a55b02ff408448e6644196e439a4 --- src/cpu/ozone/cpu_impl.hh | 1 - src/cpu/simple_thread.hh | 1 - 2 files changed, 2 deletions(-) (limited to 'src') diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index d78162243..d1214223b 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -53,7 +53,6 @@ #include "arch/vtophys.hh" #include "base/callback.hh" #include "cpu/profile.hh" -#include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 824914ad0..95848ee2c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -38,7 +38,6 @@ #include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" -#include "mem/physical.hh" #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" -- cgit v1.2.3 From 04ac944920f6ab7d74de1b4d8be8f4ae0accff4f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 28 May 2007 08:04:33 -0700 Subject: Reformat comments to meet line length restriction. --HG-- extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a --- src/mem/packet.cc | 11 ++++++----- src/mem/packet.hh | 16 +++++++++------- 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 2463a19ba..f70c0cec3 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -192,11 +192,12 @@ fixPacket(PacketPtr func, PacketPtr timing) func->flags |= SATISFIED; return false; } else { - // In this case the timing packet only partially satisfies the - // requset, so we would need more information to make this work. - // Like bytes valid in the packet or something, so the request could - // continue and get this bit of possibly newer data along with the - // older data not written to yet. + // In this case the timing packet only partially satisfies + // the request, so we would need more information to make + // this work. Like bytes valid in the packet or + // something, so the request could continue and get this + // bit of possibly newer data along with the older data + // not written to yet. panic("Timing packet only partially satisfies the functional" "request. Now what?"); } diff --git a/src/mem/packet.hh b/src/mem/packet.hh index dc23e9f6d..c1e6a1e7f 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -506,16 +506,18 @@ class Packet bool intersect(PacketPtr p); }; -/** This function given a functional packet and a timing packet either satisfies - * the timing packet, or updates the timing packet to reflect the updated state - * in the timing packet. It returns if the functional packet should continue to - * traverse the memory hierarchy or not. +/** This function given a functional packet and a timing packet either + * satisfies the timing packet, or updates the timing packet to + * reflect the updated state in the timing packet. It returns if the + * functional packet should continue to traverse the memory hierarchy + * or not. */ bool fixPacket(PacketPtr func, PacketPtr timing); -/** This function is a wrapper for the fixPacket field that toggles the hasData bit - * it is used when a response is waiting in the caches, but hasn't been marked as a - * response yet (so the fixPacket needs to get the correct value for the hasData) +/** This function is a wrapper for the fixPacket field that toggles + * the hasData bit it is used when a response is waiting in the + * caches, but hasn't been marked as a response yet (so the fixPacket + * needs to get the correct value for the hasData) */ bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing); -- cgit v1.2.3 From 41f6cbce9aa24f9cd8a6eb4a340dcc2e9671cdcb Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 28 May 2007 08:11:43 -0700 Subject: Restructure SimpleTimingPort a bit: - factor out checkFunctional() code so it can be called from derived classes - use EventWrapper for sendEvent, move event handling code from event to port where it belongs - make sendEvent a pointer so derived classes can override it - replace std::pair with new class for readability --HG-- extra : convert_revision : 5709de2daacfb751a440144ecaab5f9fc02e6b7a --- src/mem/physical.cc | 15 +--------- src/mem/tport.cc | 84 ++++++++++++++++++++++++++++------------------------- src/mem/tport.hh | 47 +++++++++++++++++++----------- 3 files changed, 76 insertions(+), 70 deletions(-) (limited to 'src') diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 6621c36cf..9d840fe69 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -414,20 +414,7 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) void PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) { - //Since we are overriding the function, make sure to have the impl of the - //check or functional accesses here. - std::list >::iterator i = transmitList.begin(); - std::list >::iterator end = transmitList.end(); - bool notDone = true; - - while (i != end && notDone) { - PacketPtr target = i->second; - // If the target contains data, and it overlaps the - // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); - i++; - } + checkFunctional(pkt); // Default implementation of SimpleTimingPort::recvFunctional() // calls recvAtomic() and throws away the latency; we can save a diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 9a4bd7967..8797cf6e6 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -31,23 +31,32 @@ #include "mem/tport.hh" void -SimpleTimingPort::recvFunctional(PacketPtr pkt) +SimpleTimingPort::checkFunctional(PacketPtr pkt) { - std::list >::iterator i = transmitList.begin(); - std::list >::iterator end = transmitList.end(); - bool notDone = true; + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); - while (i != end && notDone) { - PacketPtr target = i->second; + while (i != end) { + PacketPtr target = i->pkt; // If the target contains data, and it overlaps the // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); + if (target->intersect(pkt)) { + if (!fixPacket(pkt, target)) { + // fixPacket returns true for continue, false for done + return; + } + } i++; } +} - //Then just do an atomic access and throw away the returned latency +void +SimpleTimingPort::recvFunctional(PacketPtr pkt) +{ + checkFunctional(pkt); + + // Just do an atomic access and throw away the returned latency if (pkt->result != Packet::Success) recvAtomic(pkt); } @@ -67,12 +76,9 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) pkt->makeTimingResponse(); sendTiming(pkt, latency); } - else { - if (pkt->cmd != MemCmd::UpgradeReq) - { - delete pkt->req; - delete pkt; - } + else if (pkt->cmd != MemCmd::UpgradeReq) { + delete pkt->req; + delete pkt; } return true; } @@ -81,12 +87,12 @@ void SimpleTimingPort::recvRetry() { assert(!transmitList.empty()); - if (Port::sendTiming(transmitList.front().second)) { + if (Port::sendTiming(transmitList.front().pkt)) { transmitList.pop_front(); DPRINTF(Bus, "No Longer waiting on retry\n"); if (!transmitList.empty()) { - Tick time = transmitList.front().first; - sendEvent.schedule(time <= curTick ? curTick+1 : time); + Tick time = transmitList.front().tick; + sendEvent->schedule(time <= curTick ? curTick+1 : time); } } @@ -101,29 +107,29 @@ SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) { // Nothing is on the list: add it and schedule an event if (transmitList.empty()) { - assert(!sendEvent.scheduled()); - sendEvent.schedule(curTick+time); - transmitList.push_back(std::pair(time+curTick,pkt)); + assert(!sendEvent->scheduled()); + sendEvent->schedule(curTick+time); + transmitList.push_back(DeferredPacket(time+curTick, pkt)); return; } // something is on the list and this belongs at the end - if (time+curTick >= transmitList.back().first) { - transmitList.push_back(std::pair(time+curTick,pkt)); + if (time+curTick >= transmitList.back().tick) { + transmitList.push_back(DeferredPacket(time+curTick, pkt)); return; } // Something is on the list and this belongs somewhere else - std::list >::iterator i = transmitList.begin(); - std::list >::iterator end = transmitList.end(); + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); bool done = false; while (i != end && !done) { - if (time+curTick < i->first) { + if (time+curTick < i->tick) { if (i == transmitList.begin()) { //Inserting at begining, reschedule - sendEvent.reschedule(time+curTick); + sendEvent->reschedule(time+curTick); } - transmitList.insert(i,std::pair(time+curTick,pkt)); + transmitList.insert(i, DeferredPacket(time+curTick, pkt)); done = true; } i++; @@ -132,20 +138,20 @@ SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) } void -SimpleTimingPort::SendEvent::process() +SimpleTimingPort::processSendEvent() { - assert(port->transmitList.size()); - assert(port->transmitList.front().first <= curTick); - if (port->Port::sendTiming(port->transmitList.front().second)) { + assert(transmitList.size()); + assert(transmitList.front().tick <= curTick); + if (Port::sendTiming(transmitList.front().pkt)) { //send successful, remove packet - port->transmitList.pop_front(); - if (!port->transmitList.empty()) { - Tick time = port->transmitList.front().first; - schedule(time <= curTick ? curTick+1 : time); + transmitList.pop_front(); + if (!transmitList.empty()) { + Tick time = transmitList.front().tick; + sendEvent->schedule(time <= curTick ? curTick+1 : time); } - if (port->transmitList.empty() && port->drainEvent) { - port->drainEvent->process(); - port->drainEvent = NULL; + if (transmitList.empty() && drainEvent) { + drainEvent->process(); + drainEvent = NULL; } return; } diff --git a/src/mem/tport.hh b/src/mem/tport.hh index 3d28ea3e5..9e8a01786 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -58,9 +58,26 @@ class SimpleTimingPort : public Port { protected: + /** A deferred packet, buffered to transmit later. */ + class DeferredPacket { + public: + Tick tick; ///< The tick when the packet is ready to transmit + PacketPtr pkt; ///< Pointer to the packet to transmit + DeferredPacket(Tick t, PacketPtr p) + : tick(t), pkt(p) + {} + }; + + typedef std::list DeferredPacketList; + typedef std::list::iterator DeferredPacketIterator; + /** A list of outgoing timing response packets that haven't been * serviced yet. */ - std::list > transmitList; + DeferredPacketList transmitList; + + /** This function attempts to send deferred packets. Scheduled to + * be called in the future via SendEvent. */ + void processSendEvent(); /** * This class is used to implemented sendTiming() with a delay. When @@ -68,27 +85,19 @@ class SimpleTimingPort : public Port * When the event time expires it attempts to send the packet. * If it cannot, the packet sent when recvRetry() is called. **/ - class SendEvent : public Event - { - SimpleTimingPort *port; - - public: - SendEvent(SimpleTimingPort *p) - : Event(&mainEventQueue), port(p) - { } - - virtual void process(); - - virtual const char *description() - { return "Future scheduled sendTiming event"; } - }; + typedef EventWrapper + SendEvent; - SendEvent sendEvent; + Event *sendEvent; /** If we need to drain, keep the drain event around until we're done * here.*/ Event *drainEvent; + /** Check the list of buffered packets against the supplied + * functional request. */ + void checkFunctional(PacketPtr funcPkt); + /** Schedule a sendTiming() event to be called in the future. * @param pkt packet to send * @param time increment from now (in ticks) to send packet @@ -115,9 +124,13 @@ class SimpleTimingPort : public Port public: SimpleTimingPort(std::string pname, MemObject *_owner = NULL) - : Port(pname, _owner), sendEvent(this), drainEvent(NULL) + : Port(pname, _owner), + sendEvent(new SendEvent(this)), + drainEvent(NULL) {} + ~SimpleTimingPort() { delete sendEvent; } + /** Hook for draining timing accesses from the system. The * associated SimObject's drain() functions should be implemented * something like this when this class is used: -- cgit v1.2.3 From 365e4ac37446c0ff58b035767f8047c8a8c4fd61 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 29 May 2007 22:23:41 -0700 Subject: A little more cleanup & refactoring of SimpleTimingPort. Make it a better base class for cache ports. --HG-- extra : convert_revision : 37d6de11545a68c1a7d11ce33fe5971c51434ee4 --- src/mem/tport.cc | 88 +++++++++++++++++++++++++++++--------------------------- src/mem/tport.hh | 21 ++++++++++++-- 2 files changed, 63 insertions(+), 46 deletions(-) (limited to 'src') diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 8797cf6e6..7b1c14467 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -36,7 +36,7 @@ SimpleTimingPort::checkFunctional(PacketPtr pkt) DeferredPacketIterator i = transmitList.begin(); DeferredPacketIterator end = transmitList.end(); - while (i != end) { + for (; i != end; ++i) { PacketPtr target = i->pkt; // If the target contains data, and it overlaps the // probed request, need to update data @@ -46,8 +46,6 @@ SimpleTimingPort::checkFunctional(PacketPtr pkt) return; } } - - i++; } } @@ -74,7 +72,7 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) // turn packet around to go back to requester if response expected if (pkt->needsResponse()) { pkt->makeTimingResponse(); - sendTiming(pkt, latency); + schedSendTiming(pkt, latency); } else if (pkt->cmd != MemCmd::UpgradeReq) { delete pkt->req; @@ -83,81 +81,85 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) return true; } -void -SimpleTimingPort::recvRetry() -{ - assert(!transmitList.empty()); - if (Port::sendTiming(transmitList.front().pkt)) { - transmitList.pop_front(); - DPRINTF(Bus, "No Longer waiting on retry\n"); - if (!transmitList.empty()) { - Tick time = transmitList.front().tick; - sendEvent->schedule(time <= curTick ? curTick+1 : time); - } - } - - if (transmitList.empty() && drainEvent) { - drainEvent->process(); - drainEvent = NULL; - } -} void -SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) +SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) { + assert(when > curTick); + // Nothing is on the list: add it and schedule an event if (transmitList.empty()) { assert(!sendEvent->scheduled()); - sendEvent->schedule(curTick+time); - transmitList.push_back(DeferredPacket(time+curTick, pkt)); + sendEvent->schedule(when); + transmitList.push_back(DeferredPacket(when, pkt)); return; } // something is on the list and this belongs at the end - if (time+curTick >= transmitList.back().tick) { - transmitList.push_back(DeferredPacket(time+curTick, pkt)); + if (when >= transmitList.back().tick) { + transmitList.push_back(DeferredPacket(when, pkt)); return; } // Something is on the list and this belongs somewhere else DeferredPacketIterator i = transmitList.begin(); DeferredPacketIterator end = transmitList.end(); - bool done = false; - while (i != end && !done) { - if (time+curTick < i->tick) { + for (; i != end; ++i) { + if (when < i->tick) { if (i == transmitList.begin()) { //Inserting at begining, reschedule - sendEvent->reschedule(time+curTick); + sendEvent->reschedule(when); } - transmitList.insert(i, DeferredPacket(time+curTick, pkt)); - done = true; + transmitList.insert(i, DeferredPacket(when, pkt)); + return; } - i++; } - assert(done); + assert(false); // should never get here } + void -SimpleTimingPort::processSendEvent() +SimpleTimingPort::sendDeferredPacket() { - assert(transmitList.size()); - assert(transmitList.front().tick <= curTick); - if (Port::sendTiming(transmitList.front().pkt)) { + assert(deferredPacketReady()); + bool success = sendTiming(transmitList.front().pkt); + + if (success) { //send successful, remove packet transmitList.pop_front(); if (!transmitList.empty()) { Tick time = transmitList.front().tick; sendEvent->schedule(time <= curTick ? curTick+1 : time); } + if (transmitList.empty() && drainEvent) { drainEvent->process(); drainEvent = NULL; } - return; } - // send unsuccessful (due to flow control). Will get retry - // callback later; save for then if not already - DPRINTF(Bus, "Waiting on retry\n"); + + waitingOnRetry = !success; + + if (waitingOnRetry) { + DPRINTF(Bus, "Send failed, waiting on retry\n"); + } +} + + +void +SimpleTimingPort::recvRetry() +{ + DPRINTF(Bus, "Received retry\n"); + assert(waitingOnRetry); + sendDeferredPacket(); +} + + +void +SimpleTimingPort::processSendEvent() +{ + assert(!waitingOnRetry); + sendDeferredPacket(); } diff --git a/src/mem/tport.hh b/src/mem/tport.hh index 9e8a01786..ea0f05ed1 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -94,15 +94,29 @@ class SimpleTimingPort : public Port * here.*/ Event *drainEvent; + /** Remember whether we're awaiting a retry from the bus. */ + bool waitingOnRetry; + /** Check the list of buffered packets against the supplied * functional request. */ void checkFunctional(PacketPtr funcPkt); + /** Check whether we have a packet ready to go on the transmit list. */ + bool deferredPacketReady() + { return !transmitList.empty() && transmitList.front().tick <= curTick; } + /** Schedule a sendTiming() event to be called in the future. * @param pkt packet to send - * @param time increment from now (in ticks) to send packet + * @param absolute time (in ticks) to send packet + */ + void schedSendTiming(PacketPtr pkt, Tick when); + + /** Attempt to send the packet at the head of the deferred packet + * list. Caller must guarantee that the deferred packet list is + * non-empty and that the head packet is scheduled for curTick (or + * earlier). */ - void sendTiming(PacketPtr pkt, Tick time); + void sendDeferredPacket(); /** This function is notification that the device should attempt to send a * packet again. */ @@ -126,7 +140,8 @@ class SimpleTimingPort : public Port SimpleTimingPort(std::string pname, MemObject *_owner = NULL) : Port(pname, _owner), sendEvent(new SendEvent(this)), - drainEvent(NULL) + drainEvent(NULL), + waitingOnRetry(false) {} ~SimpleTimingPort() { delete sendEvent; } -- cgit v1.2.3 From 4e65d2678d0778915688f3b276543c357b4618ed Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 30 May 2007 01:53:28 -0400 Subject: tport.cc: Oops... forgot to update call site after changing function argument semantics. src/mem/tport.cc: Oops... forgot to update call site after changing function argument semantics. --HG-- extra : convert_revision : 9234b991dc678f062d268ace73c71b3d13dd17dc --- src/mem/tport.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 7b1c14467..ed4c0c172 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -72,7 +72,7 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) // turn packet around to go back to requester if response expected if (pkt->needsResponse()) { pkt->makeTimingResponse(); - schedSendTiming(pkt, latency); + schedSendTiming(pkt, curTick + latency); } else if (pkt->cmd != MemCmd::UpgradeReq) { delete pkt->req; -- cgit v1.2.3 From 7797a239cc80561f9a29953fc068a562b942bd33 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 30 May 2007 17:19:20 -0700 Subject: Fix cut-n-pasto to make the path correct --HG-- extra : convert_revision : a6194cc9c3b2eb83dc8480ed0417b2246f07b4bd --- src/cpu/o3/SConscript | 2 +- src/cpu/ozone/SConscript | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index a1af620be..ad61ad228 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -75,7 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) if env['USE_CHECKER']: - SimObject('m5/objects/O3Checker.py') + SimObject('O3Checker.py') Source('checker_builder.cc') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index 601e80a72..cb2006456 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -45,5 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_lsq.cc') Source('rename_table.cc') if env['USE_CHECKER']: - SimObject('m5/objects/OzoneChecker.py') + SimObject('OzoneChecker.py') Source('checker_builder.cc') -- cgit v1.2.3 From ecf1eb72489524c54897275c6ea314fe500c2b7d Mon Sep 17 00:00:00 2001 From: Vincentius Robby Date: Thu, 31 May 2007 16:01:41 -0400 Subject: Assign traceData to be NULL at BaseSimpleCPU constructor. Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/arch/sparc/miscregfile.cc: Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/cpu/simple/base.cc: Assign traceData to be NULL at BaseSimpleCPU constructor. Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries --HG-- extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6 --- src/arch/sparc/miscregfile.cc | 60 ++++++++++++++++++++++++++----------------- src/cpu/simple/base.cc | 16 +++++++----- 2 files changed, 46 insertions(+), 30 deletions(-) (limited to 'src') diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index f511ef454..0300694cc 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -142,27 +142,38 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - switch (miscReg) { - case MISCREG_TLB_DATA: - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] //case MISCREG_Y: // return y; //case MISCREG_CCR: @@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return tl; case MISCREG_PIL: return pil; - case MISCREG_CWP: - return cwp; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; //case MISCREG_CANSAVE: // return cansave; //case MISCREG_CANRESTORE: @@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) // return otherwin; //case MISCREG_WSTATE: // return wstate; - case MISCREG_GL: - return gl; + //case MISCREG_GL: + // return gl; /** Hyper privileged registers */ case MISCREG_HPSTATE: diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4fed2059b..aa341487c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,7 @@ using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(Params *p) - : BaseCPU(p), thread(NULL), predecoder(NULL) + : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) { #if FULL_SYSTEM thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); @@ -326,18 +326,20 @@ BaseSimpleCPU::checkForInterrupts() Fault BaseSimpleCPU::setupFetchRequest(Request *req) { + uint64_t threadPC = thread->readPC(); + // set up memory request for instruction fetch #if ISA_HAS_DELAY_SLOT - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, thread->readNextPC(),thread->readNextNPC()); #else - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC, thread->readNextPC()); #endif - req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), - (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, - thread->readPC()); + req->setVirt(0, threadPC & ~3, sizeof(MachInst), + (FULL_SYSTEM && (threadPC & 1)) ? PHYSICAL : 0, + threadPC); Fault fault = thread->translateInstReq(req); @@ -396,6 +398,7 @@ BaseSimpleCPU::preExecute() fetchMicroOp(thread->readMicroPC()); } +#if TRACING_ON //If we decoded an instruction this "tick", record information about it. if(curStaticInst) { @@ -409,6 +412,7 @@ BaseSimpleCPU::preExecute() thread->setInst(inst); #endif // FULL_SYSTEM } +#endif // TRACING_ON } void -- cgit v1.2.3