From cf0e202cbad9823bdd3361164f4b2ee41c4c1501 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Sat, 24 Feb 2007 22:05:01 -0500
Subject: make m5 readfile work on solaris... we can have a solaris regression
soon!
src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
---
src/arch/sparc/isa/decoder.isa | 5 +++++
src/arch/sparc/isa/operands.isa | 12 ++++++------
2 files changed, 11 insertions(+), 6 deletions(-)
(limited to 'src')
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index e2d1707dd..c07295248 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1014,6 +1014,11 @@ decode OP default Unknown::unknown()
// we have 7 bits of space here to play with...
0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
}}, No_OpClass, IsNonSpeculative);
+ 0x50: m5readfile({{
+ O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
+ }}, IsNonSpeculative);
+ 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
+ }}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, No_OpClass, IsNonSpeculative);
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 82e9407de..092544aab 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,12 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
- 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
- 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
- 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
- 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
- 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
- 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
+ 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
+ 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
+ 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
+ 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13),
+ 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14),
+ 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
--
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