From d093fcb07924cc4341b8142c448b905dd94f7125 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 12 Jun 2008 00:35:50 -0400 Subject: CPU: Make the simple cpu trace data for loads/stores. --- src/cpu/simple/atomic.cc | 6 ++++++ src/cpu/simple/timing.cc | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'src') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 23bd40b9b..acd280568 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -355,6 +355,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) if (secondAddr <= addr) { data = gtoh(data); + if (traceData) { + traceData->setData(data); + } return fault; } @@ -568,6 +571,9 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // If the write needs to have a fault on the access, consider // calling changeStatus() and changing it to "bad addr write" // or something. + if (traceData) { + traceData->setData(data); + } return fault; } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index a76824ff3..d0c7dd787 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -296,6 +296,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) delete req; } + if (traceData) { + traceData->setData(data); + } return fault; } @@ -431,6 +434,9 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) delete req; } + if (traceData) { + traceData->setData(data); + } // If the write needs to have a fault on the access, consider calling // changeStatus() and changing it to "bad addr write" or something. -- cgit v1.2.3