From e36839e7780df11065ab0a08abaf3fcf68135aa7 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 8 Mar 2019 10:47:02 +0000 Subject: dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0) For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini Reviewed-by: Ciro Santilli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/dev/arm/gic_v3_distributor.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 148de5a19..f261b295b 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -578,6 +578,10 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size, // Interrupt Clear-Enable Registers int first_intid = (addr - GICD_ICENABLER.start()) * 8; + if (isNotSPI(first_intid)) { + return; + } + for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines; i++, int_id++) { -- cgit v1.2.3