From e758c1fc0404fca9e95139ed98ee422c43742c97 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 12 Jul 2006 17:18:34 -0400
Subject: Serialization changes to make O3CPU consistent with the other models.

src/cpu/o3/commit_impl.hh:
    Always set instruction.  This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
    Change serialization so it matches other CPU's output.  Also fix up some indexing.

--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
---
 src/cpu/o3/commit_impl.hh | 12 ++++++------
 src/cpu/o3/cpu.cc         | 15 ++++++++++-----
 2 files changed, 16 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 904af1071..c667d633a 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -996,6 +996,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
     // Check if the instruction caused a fault.  If so, trap.
     Fault inst_fault = head_inst->getFault();
 
+    // DTB will sometimes need the machine instruction for when
+    // faults happen.  So we will set it here, prior to the DTB
+    // possibly needing it for its fault.
+    thread[tid]->setInst(
+        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
+
     if (inst_fault != NoFault) {
         head_inst->setCompleted();
         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
@@ -1018,12 +1024,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         // execution doesn't generate extra squashes.
         thread[tid]->inSyscall = true;
 
-        // DTB will sometimes need the machine instruction for when
-        // faults happen.  So we will set it here, prior to the DTB
-        // possibly needing it for its fault.
-        thread[tid]->setInst(
-            static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
-
         // Execute the trap.  Although it's slightly unrealistic in
         // terms of timing (as it doesn't wait for the full timing of
         // the trap event to complete before updating state), it's
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7d2727401..de87ee2ef 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -765,7 +765,8 @@ template <class Impl>
 void
 FullO3CPU<Impl>::serialize(std::ostream &os)
 {
-    SERIALIZE_ENUM(_status);
+    SimObject::State so_state = SimObject::getState();
+    SERIALIZE_ENUM(so_state);
     BaseCPU::serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
@@ -786,7 +787,8 @@ template <class Impl>
 void
 FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 {
-    UNSERIALIZE_ENUM(_status);
+    SimObject::State so_state;
+    UNSERIALIZE_ENUM(so_state);
     BaseCPU::unserialize(cp, section);
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 
@@ -1063,7 +1065,8 @@ template <class Impl>
 void
 FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
 {
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
 
     regFile.setFloatReg(phys_reg, val);
 }
@@ -1072,7 +1075,8 @@ template <class Impl>
 void
 FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
 {
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
 
     regFile.setFloatReg(phys_reg, val, 64);
 }
@@ -1081,7 +1085,8 @@ template <class Impl>
 void
 FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
 {
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
 
     regFile.setFloatRegBits(phys_reg, val);
 }
-- 
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