From ef9fc010736df313fbc7acaea3a9b0e2fee33955 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 03:44:25 -0500 Subject: MEM: Clean-up of Functional/Virtual/TranslatingPort remnants This patch cleans up forward declarations and a member-function prototype that still referred to the old FunctionalPort, VirtualPort and TranslatingPort. There is no change in functionality. --- src/arch/arm/vtophys.hh | 1 - src/arch/mips/vtophys.hh | 1 - src/arch/power/vtophys.hh | 1 - src/arch/sparc/vtophys.hh | 4 ---- src/cpu/inorder/thread_context.hh | 2 -- src/cpu/o3/thread_context.hh | 2 -- src/cpu/simple_thread.hh | 3 --- src/kern/solaris/solaris.hh | 2 -- 8 files changed, 16 deletions(-) (limited to 'src') diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh index a85209a4a..12a6c6ec6 100644 --- a/src/arch/arm/vtophys.hh +++ b/src/arch/arm/vtophys.hh @@ -38,7 +38,6 @@ #include "arch/arm/utility.hh" class ThreadContext; -class FunctionalPort; namespace ArmISA { inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh index 5ecc30b1f..741ac36bc 100644 --- a/src/arch/mips/vtophys.hh +++ b/src/arch/mips/vtophys.hh @@ -38,7 +38,6 @@ #include "arch/mips/utility.hh" class ThreadContext; -class FunctionalPort; namespace MipsISA { inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh index 7371f38a6..1e8caf803 100644 --- a/src/arch/power/vtophys.hh +++ b/src/arch/power/vtophys.hh @@ -40,7 +40,6 @@ #include "arch/power/utility.hh" class ThreadContext; -class FunctionalPort; namespace PowerISA { diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh index f55967b53..7c1d23e80 100644 --- a/src/arch/sparc/vtophys.hh +++ b/src/arch/sparc/vtophys.hh @@ -36,13 +36,9 @@ #include "arch/sparc/pagetable.hh" class ThreadContext; -class FunctionalPort; namespace SparcISA { -PageTableEntry -kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr); - Addr vtophys(Addr vaddr); Addr vtophys(ThreadContext *tc, Addr vaddr); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 5b67d7e8b..058f58ffb 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -44,8 +44,6 @@ namespace Kernel { class Statistics; }; -class TranslatingPort; - /** * Derived ThreadContext class for use with the InOrderCPU. It * provides the interface for any external objects to access a diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 6ac745770..0205c63ef 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -40,8 +40,6 @@ namespace Kernel { class Statistics; }; -class TranslatingPort; - /** * Derived ThreadContext class for use with the O3CPU. It * provides the interface for any external objects to access a diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index ebc23276a..57e83b4d1 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -58,8 +58,6 @@ class BaseCPU; class FunctionProfile; class ProfileNode; -class FunctionalPort; -class PhysicalPort; namespace TheISA { namespace Kernel { @@ -71,7 +69,6 @@ namespace TheISA { #include "mem/page_table.hh" #include "sim/process.hh" -class TranslatingPort; #endif // FULL_SYSTEM diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh index 00eee994b..c6fb93f04 100644 --- a/src/kern/solaris/solaris.hh +++ b/src/kern/solaris/solaris.hh @@ -42,8 +42,6 @@ class Solaris {}; #include "kern/operatingsystem.hh" -class TranslatingPort; - /// /// This class encapsulates the types, structures, constants, /// functions, and syscall-number mappings specific to the Solaris -- cgit v1.2.3 From cfc268ad9e5b83cac551cae118811e5c86382d9e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 05:38:24 -0500 Subject: MEM: Make the RubyPort physMemPort a PioPort instead of M5Port This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system. --- src/mem/ruby/system/RubyPort.cc | 3 +-- src/mem/ruby/system/RubyPort.hh | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index b60ca2a07..af414f17a 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx) // RubyPort should only have one port to physical memory assert (physMemPort == NULL); - physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, - ruby_system, access_phys_mem); + physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this); return physMemPort; } diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 2ffdef3d9..6df713a13 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -155,7 +155,7 @@ class RubyPort : public MemObject uint16_t m_port_id; uint64_t m_request_cnt; - M5Port* physMemPort; + PioPort* physMemPort; /*! Vector of CPU Port attached to this Ruby port. */ typedef std::vector::iterator CpuPortIter; -- cgit v1.2.3