From f4e27c3ff56894e738bd2a975646b5a07d9ea75c Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Tue, 19 Dec 2017 16:58:33 +0000 Subject: arch-arm: Fault when dc ivac is executed from EL0 A previous change enabled execution of dc ivac from EL0 when SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data cache maintenance operation by VA that cannot be executed from EL0. This changeset essential reverts the change: 8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1 Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c Reviewed-by: Jack Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/7823 Maintainer: Andreas Sandberg --- src/arch/arm/miscregs.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index a9031fe0e..c0b6aa5d5 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -922,8 +922,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) if (el == EL0 && !sctlr.dze) return false; } - if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt || - reg == MISCREG_DC_IVAC_Xt) { + if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); if (el == EL0 && !sctlr.uci) return false; @@ -3557,7 +3556,7 @@ ISA::initializeMiscRegMetadata() .writes(1).exceptUserMode(); InitReg(MISCREG_DC_IVAC_Xt) .warnNotFail() - .writes(1); + .writes(1).exceptUserMode(); InitReg(MISCREG_DC_ISW_Xt) .warnNotFail() .writes(1).exceptUserMode(); -- cgit v1.2.3