From ff5718f042ecccee694ae79c9386a589fd77e8ef Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 9 Jul 2012 12:35:30 -0400 Subject: Fix: Address a few benign memory leaks This patch is the result of static analysis identifying a number of memory leaks. The leaks are all benign as they are a result of not deallocating memory in the desctructor. The fix still has value as it removes false positives in the static analysis. --- src/base/loader/hex_file.cc | 2 ++ src/cpu/activity.cc | 5 +++++ src/cpu/activity.hh | 1 + src/cpu/base.cc | 3 +++ src/cpu/o3/regfile.hh | 12 ++++++++++++ src/dev/arm/pl111.cc | 5 +++++ src/dev/arm/pl111.hh | 1 + src/dev/ethertap.cc | 1 + src/dev/i8254xGBe.cc | 7 +++++++ src/dev/i8254xGBe.hh | 2 +- src/dev/ns_gige.cc | 4 +++- src/mem/cache/mshr.cc | 2 ++ src/mem/cache/tags/fa_lru.cc | 8 ++++++++ src/mem/cache/tags/fa_lru.hh | 1 + src/mem/cache/tags/iic.cc | 1 + src/mem/page_table.cc | 1 + src/sim/serialize.cc | 4 ++++ src/sim/serialize.hh | 1 + 18 files changed, 59 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/base/loader/hex_file.cc b/src/base/loader/hex_file.cc index bfebc1b44..e26ac31e6 100755 --- a/src/base/loader/hex_file.cc +++ b/src/base/loader/hex_file.cc @@ -56,6 +56,8 @@ HexFile::HexFile(const string _filename) HexFile::~HexFile() { + if (fp != NULL) + fclose(fp); } bool diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc index 13613cffc..87875c683 100644 --- a/src/cpu/activity.cc +++ b/src/cpu/activity.cc @@ -46,6 +46,11 @@ ActivityRecorder::ActivityRecorder(const string &name, int num_stages, std::memset(stageActive, 0, numStages); } +ActivityRecorder::~ActivityRecorder() +{ + delete[] stageActive; +} + void ActivityRecorder::activity() { diff --git a/src/cpu/activity.hh b/src/cpu/activity.hh index f119c95cc..7913bf5e7 100644 --- a/src/cpu/activity.hh +++ b/src/cpu/activity.hh @@ -54,6 +54,7 @@ class ActivityRecorder public: ActivityRecorder(const std::string &name, int num_stages, int longest_latency, int count); + ~ActivityRecorder(); /** Records that there is activity this cycle. */ void activity(); diff --git a/src/cpu/base.cc b/src/cpu/base.cc index c942cad44..4017140a5 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -243,6 +243,9 @@ BaseCPU::enableFunctionTrace() BaseCPU::~BaseCPU() { + delete profileEvent; + delete[] comLoadEventQueue; + delete[] comInstEventQueue; } void diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 117c955c2..d0f50c85c 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -75,6 +75,11 @@ class PhysRegFile PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs); + /** + * Destructor to free resources + */ + ~PhysRegFile(); + //Everything below should be pretty well identical to the normal //register file that exists within AlphaISA class. //The duplication is unfortunate but it's better than having @@ -197,4 +202,11 @@ PhysRegFile::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); } +template +PhysRegFile::~PhysRegFile() +{ + delete intRegFile; + delete floatRegFile; +} + #endif diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc index 7c25958e0..c1edc29ea 100644 --- a/src/dev/arm/pl111.cc +++ b/src/dev/arm/pl111.cc @@ -84,6 +84,11 @@ Pl111::Pl111(const Params *p) vncserver->setFramebufferAddr(dmaBuffer); } +Pl111::~Pl111() +{ + delete[] dmaBuffer; +} + // read registers and frame buffer Tick Pl111::read(PacketPtr pkt) diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh index e0a03641c..36dfc46c1 100644 --- a/src/dev/arm/pl111.hh +++ b/src/dev/arm/pl111.hh @@ -316,6 +316,7 @@ class Pl111: public AmbaDmaDevice return dynamic_cast(_params); } Pl111(const Params *p); + ~Pl111(); virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); diff --git a/src/dev/ethertap.cc b/src/dev/ethertap.cc index 2a85aa524..94e381a8e 100644 --- a/src/dev/ethertap.cc +++ b/src/dev/ethertap.cc @@ -147,6 +147,7 @@ EtherTap::~EtherTap() if (buffer) delete [] buffer; + delete interface; delete listener; } diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 29bd5adc2..1f2c92425 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -122,6 +122,11 @@ IGbE::IGbE(const Params *p) txFifo.clear(); } +IGbE::~IGbE() +{ + delete etherInt; +} + void IGbE::init() { @@ -827,6 +832,8 @@ template IGbE::DescCache::~DescCache() { reset(); + delete[] fetchBuf; + delete[] wbBuf; } template diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 7c31222ed..a6b20a2bf 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -518,7 +518,7 @@ class IGbE : public EtherDevice } IGbE(const Params *params); - ~IGbE() {} + ~IGbE(); virtual void init(); virtual EtherInt *getEthPort(const std::string &if_name, int idx); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 4dc4aeae9..4a459c6c6 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -135,7 +135,9 @@ NSGigE::NSGigE(Params *p) } NSGigE::~NSGigE() -{} +{ + delete interface; +} /** * This is to write to the PCI general configuration registers diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc index ab891296f..6fa22c9b4 100644 --- a/src/mem/cache/mshr.cc +++ b/src/mem/cache/mshr.cc @@ -460,4 +460,6 @@ MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const MSHR::~MSHR() { + delete[] targets; + delete[] deferredTargets; } diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 873883c1b..3a1246ce7 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -98,6 +98,14 @@ FALRU::FALRU(unsigned _blkSize, unsigned _size, unsigned hit_latency) //assert(check()); } +FALRU::~FALRU() +{ + if (numCaches) + delete[] cacheBoundaries; + + delete[] blks; +} + void FALRU::regStats(const string &name) { diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 78f9ce1b4..fa1f49a42 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -156,6 +156,7 @@ public: * @param hit_latency The hit latency of the cache. */ FALRU(unsigned blkSize, unsigned size, unsigned hit_latency); + ~FALRU(); /** * Register the stats for this object. diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 260b89194..d6ddf04a6 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -160,6 +160,7 @@ IIC::~IIC() delete [] dataStore; delete [] tagStore; delete [] sets; + delete [] dataBlks; } /* register cache stats */ diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index f47e73c74..be862e429 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -228,6 +228,7 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) entry = new TheISA::TlbEntry(); entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); pTable[vaddr] = *entry; + delete entry; ++i; } } diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index 30655e692..54b7926d6 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -613,6 +613,10 @@ Checkpoint::Checkpoint(const string &cpt_dir) } } +Checkpoint::~Checkpoint() +{ + delete db; +} bool Checkpoint::find(const string §ion, const string &entry, string &value) diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh index 46e546be4..fdb0f4033 100644 --- a/src/sim/serialize.hh +++ b/src/sim/serialize.hh @@ -254,6 +254,7 @@ class Checkpoint public: Checkpoint(const std::string &cpt_dir); + ~Checkpoint(); const std::string cptDir; -- cgit v1.2.3