From b8612cbda3625e27f109469a1f5416237c97fb41 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 14 Nov 2003 10:52:42 -0500 Subject: Import changeset --- system/alpha/palcode/Makefile | 157 + system/alpha/palcode/cserve.h | 107 + system/alpha/palcode/dc21164.h | 961 +++++ system/alpha/palcode/dc21164FromGasSources.h | 965 +++++ system/alpha/palcode/ev5_alpha_defs.h | 323 ++ system/alpha/palcode/ev5_defs.h | 575 +++ system/alpha/palcode/ev5_impure.h | 392 ++ system/alpha/palcode/ev5_osfalpha_defs.h | 160 + system/alpha/palcode/ev5_paldef.h | 185 + system/alpha/palcode/fromHudsonMacros.h | 145 + system/alpha/palcode/fromHudsonOsf.h | 554 +++ system/alpha/palcode/macros.h | 137 + system/alpha/palcode/osf.h | 545 +++ system/alpha/palcode/osfpal.nh | 0 system/alpha/palcode/osfpal.s | 5123 ++++++++++++++++++++++++++ system/alpha/palcode/platform.h | 251 ++ system/alpha/palcode/platform_srcmax.s | 1825 +++++++++ system/alpha/palcode/platform_tlaser.s | 2814 ++++++++++++++ system/alpha/palcode/simos.h | 16 + system/alpha/palcode/xxm.sed | 5 + 20 files changed, 15240 insertions(+) create mode 100644 system/alpha/palcode/Makefile create mode 100644 system/alpha/palcode/cserve.h create mode 100644 system/alpha/palcode/dc21164.h create mode 100644 system/alpha/palcode/dc21164FromGasSources.h create mode 100644 system/alpha/palcode/ev5_alpha_defs.h create mode 100644 system/alpha/palcode/ev5_defs.h create mode 100644 system/alpha/palcode/ev5_impure.h create mode 100644 system/alpha/palcode/ev5_osfalpha_defs.h create mode 100644 system/alpha/palcode/ev5_paldef.h create mode 100644 system/alpha/palcode/fromHudsonMacros.h create mode 100644 system/alpha/palcode/fromHudsonOsf.h create mode 100644 system/alpha/palcode/macros.h create mode 100644 system/alpha/palcode/osf.h create mode 100644 system/alpha/palcode/osfpal.nh create mode 100644 system/alpha/palcode/osfpal.s create mode 100644 system/alpha/palcode/platform.h create mode 100644 system/alpha/palcode/platform_srcmax.s create mode 100644 system/alpha/palcode/platform_tlaser.s create mode 100644 system/alpha/palcode/simos.h create mode 100644 system/alpha/palcode/xxm.sed (limited to 'system/alpha/palcode') diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile new file mode 100644 index 000000000..7d4f21cd1 --- /dev/null +++ b/system/alpha/palcode/Makefile @@ -0,0 +1,157 @@ +# +# $Id: Makefile,v 1.2 1997/12/16 01:18:38 bugnion Exp $ +# +# Revision History: +# +# $Log: Makefile,v $ +# Revision 1.2 1997/12/16 01:18:38 bugnion +# Removed bogus TLASER offsets from palcode build. -- roll over +# simultaneously with the simulation tree +# +# Revision 1.1.1.1 1997/10/30 23:27:18 verghese +# current 10/29/97 +# +# +# Set environment variables to point to various things: +# +# EB_TOOLBOX - Where your toolset is located +# + +EB_TOOLBOX = /wrl/proj/simos/bin/tools/osf +CPP = /usr/bin/cpp +AS = $(EB_TOOLBOX)/gas +LD = $(EB_TOOLBOX)/gld +DIS = $(EB_TOOLBOX)/alist +STRIP = $(EB_TOOLBOX)/astrip +PVC = $(EB_TOOLBOX)/pvc +MAKEDEP = $(CPP) -MM + +# +# Define KDEBUG if you want a special unprivileged CALL_PAL +# breakpoint trap handler for remote kernel debugging. +# +# Define CONSOLE_ENTRY to change the sys$enter_console +# transfer address. Default CONSOLE_ENTRY value is 0x10000. +# +# Define DISABLE_CRD to disable CRD. Note that reset sets MCES so that +# correctable errors are ignored anyway, but this actually stops the +# interrupt. +# + +DEFINES = -DDISABLE_CRD -DSIMOS -DBUILD_PALCODE +DEFINES += -I$(SIMTOOLS)/cpus-alpha/simos + +CPPFLAGS = +ASFLAGS = -21164 +#LDFLAGS = -Tstrip 0 -Thdr -N +#LDFLAGS = -Tstrip 2000 -Thdr -N # removed bugnion +LDFLAGS = -Tstrip 4000 -Thdr -N +# Source files: +# +# This is the only block in which the list of source files should change. +# +# SFILES - assembler source files +# HFILES - header files +# + +SFILES = osfpal.s platform.s + +HFILES = dc21164.h \ + osf.h \ + macros.h \ + ev5_impure.h \ + cserve.h \ + platform.h + +# Intermediate files: +# +# This block should not change. +# + +IFILES = $(SFILES:.s=.i) + +# Object files: +# +# This block should not change. +# + +OFILES = $(IFILES:.i=.o) + +.DEFAULT: + co -u $< + +.SUFFIXES: +.SUFFIXES: .s .i .o + +.s.i: + $(CPP) $(CPPFLAGS) $(DEFINES) $< $*.i + +osfpal.nh: osfpal + $(STRIP) -a osfpal $@ + $(DIS) osfpal >osfpal.dis + +osfpal: $(OFILES) + echo '$OFILES= ' $(OFILES) + $(LD) $(LDFLAGS) -o $@ $(OFILES) + +osfpal.o: osfpal.i + $(AS) $(ASFLAGS) -o $@ osfpal.i + +platform.o: platform.i + $(AS) $(ASFLAGS) -o $@ platform.i + +pvc: osfpal.lis osfpal.nh osfpal.ent osfpal.map + (export PVC_PAL PVC_ENTRY PVC_MAP PVC_CPU; \ + PVC_PAL=osfpal.nh; \ + PVC_ENTRY=osfpal.ent; \ + PVC_MAP=osfpal.map; \ + PVC_CPU=ev5; \ + $(PVC);) + +osfpal.lis: osfpal + $(DIS) osfpal > $@ + +osfpal.map: osfpal + $(DIS) -m osfpal > $@ + +depend: + @cat < /dev/null > makedep + @(for i in $(SFILES); do echo $$i; \ + $(MAKEDEP) $(DEFINES) $$i | \ + awk '{ if ($$1 != prev) {if (rec != "") print rec; \ + rec = $$0; prev = $$1; } \ + else { if (length(rec $$2) > 78) { print rec; rec = $$0; } \ + else rec = rec " " $$2 } } \ + END { print rec }' | sed 's/\.o/\.i/' \ + >> makedep; done) + @echo '/^# DO NOT DELETE THIS LINE/+1,$$d' > eddep + @echo '$$r makedep' >> eddep + @echo 'w' >> eddep + @cp Makefile Makefile.bak + @ed - Makefile < eddep + @rm -f eddep makedep + @echo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile + @echo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile + @echo '# see make depend above' >> Makefile + +clean: + rm -f core $(OFILES) $(IFILES) + +clobber: clean + rm -f osfpal.lis osfpal.nh osfpal.map osfpal + +rcsinfo: + rlog RCS/* + +rcsget: + co -u $(HFILES) $(SFILES) + +# DO NOT DELETE THIS LINE +osfpal.i: osfpal.s +platform.i: platform.s ./cserve.h ./platform.h +# DEPENDENCIES MUST END AT END OF FILE +# IF YOU PUT STUFF HERE IT WILL GO AWAY +# see make depend above + + + diff --git a/system/alpha/palcode/cserve.h b/system/alpha/palcode/cserve.h new file mode 100644 index 000000000..47a30a0a3 --- /dev/null +++ b/system/alpha/palcode/cserve.h @@ -0,0 +1,107 @@ +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:20 1995] SF: [cserve.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __CSERVE_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 OSF/1 PALcode +** +** MODULE: +** +** cserve.h +** +** MODULE DESCRIPTION: +** +** Platform specific cserve definitions. +** +** AUTHOR: ES +** +** CREATION DATE: 21-JUN-1994 +** +** $Id: cserve.h,v 1.1.1.1 1997/10/30 23:27:18 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: cserve.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:18 verghese +** current 10/29/97 +** +** Revision 1.6 1995/04/03 17:29:52 samberg +** Add rd_bccfg_off +** +** Revision 1.5 1995/02/02 19:31:34 samberg +** Added WR_BCACHE, deleted WR_BCCFG and WR_BCCTL +** +** Revision 1.4 1994/12/08 17:13:34 samberg +** Add CSERVE_K_WR_BCCTL and CSERVE_K_WR_BCCFG +** +** Revision 1.3 1994/11/30 15:59:30 samberg +** Use c-style comments for c compiler use +** +** Revision 1.2 1994/11/22 19:02:46 samberg +** Add constants for ev4 backward compatibility +** +** Revision 1.2 1994/11/22 19:02:46 samberg +** Add constants for ev4 backward compatibility +** +** Revision 1.1 1994/07/08 17:01:40 samberg +** Initial revision +** +** +*/ + +/* +** Console Service (cserve) sub-function codes: +*/ +#define CSERVE_K_LDQP 0x01 +#define CSERVE_K_STQP 0x02 +#define CSERVE_K_JTOPAL 0x09 +#define CSERVE_K_WR_INT 0x0A +#define CSERVE_K_RD_IMPURE 0x0B +#define CSERVE_K_PUTC 0x0F +#define CSERVE_K_WR_ICSR 0x10 +#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_ICSR 0x11 +#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_BCCTL 0x12 +#define CSERVE_K_RD_BCCFG 0x13 + +#define CSERVE_K_WR_BCACHE 0x16 + +#define CSERVE_K_RD_BCCFG_OFF 0x17 +#define CSERVE_K_JTOKERN 0x18 + + diff --git a/system/alpha/palcode/dc21164.h b/system/alpha/palcode/dc21164.h new file mode 100644 index 000000000..4bdb118c0 --- /dev/null +++ b/system/alpha/palcode/dc21164.h @@ -0,0 +1,961 @@ +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:11 1995] SF: [dc21164.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __DC21164_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** dc21164.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: dc21164.h,v 1.1.1.1 1997/10/30 23:27:18 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: dc21164.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:18 verghese +** current 10/29/97 +** +** Revision 1.15 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.14 1995/03/20 14:55:23 samberg +** Add flushIc to make Roger Cruz's life easier. +** +** Revision 1.13 1994/12/14 15:52:48 samberg +** Add slXmit and slRcv bit definitions +** +** Revision 1.12 1994/09/07 15:43:49 samberg +** Changes for Makefile.vpp, take out OSF definition +** +** Revision 1.11 1994/07/26 17:38:35 samberg +** Changes for SD164. +** +** Revision 1.10 1994/07/08 17:02:12 samberg +** Changes to support platform specific additions +** +** Revision 1.8 1994/05/31 15:49:21 ericr +** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows +** +** Revision 1.7 1994/05/26 19:29:51 ericr +** Added BC_CONFIG definitions +** +** Revision 1.6 1994/05/25 14:27:25 ericr +** Added physical bit to ldq_lp and stq_cp macros +** +** Revision 1.5 1994/05/20 18:07:50 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.4 1994/01/17 21:46:54 ericr +** Added floating point register definitions +** +** Revision 1.3 1994/01/03 19:31:49 ericr +** Added cache parity error status register definitions +** +** Revision 1.2 1993/12/22 20:42:35 eric +** Added ptTrap, ptMisc and flag definitions +** Added PAL shadow regsiter definitions +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +#define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +#define sirr 0x108 /* RW - Software Interrupt Request */ +#define astrr 0x109 /* RW - Async. System Trap Request */ +#define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +#define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +#define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF< = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +#define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + diff --git a/system/alpha/palcode/dc21164FromGasSources.h b/system/alpha/palcode/dc21164FromGasSources.h new file mode 100644 index 000000000..9b3389269 --- /dev/null +++ b/system/alpha/palcode/dc21164FromGasSources.h @@ -0,0 +1,965 @@ +#ifndef DC21164FROMGASSOURCES_INCLUDED +#define DC21164FROMGASSOURCES_INCLUDED 1 + +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** dc21164.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: dc21164FromGasSources.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:45:46 boyle +** Initial revision +** +** Revision 1.15 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.14 1995/03/20 14:55:23 samberg +** Add flushIc to make Roger Cruz's life easier. +** +** Revision 1.13 1994/12/14 15:52:48 samberg +** Add slXmit and slRcv bit definitions +** +** Revision 1.12 1994/09/07 15:43:49 samberg +** Changes for Makefile.vpp, take out OSF definition +** +** Revision 1.11 1994/07/26 17:38:35 samberg +** Changes for SD164. +** +** Revision 1.10 1994/07/08 17:02:12 samberg +** Changes to support platform specific additions +** +** Revision 1.8 1994/05/31 15:49:21 ericr +** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows +** +** Revision 1.7 1994/05/26 19:29:51 ericr +** Added BC_CONFIG definitions +** +** Revision 1.6 1994/05/25 14:27:25 ericr +** Added physical bit to ldq_lp and stq_cp macros +** +** Revision 1.5 1994/05/20 18:07:50 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.4 1994/01/17 21:46:54 ericr +** Added floating point register definitions +** +** Revision 1.3 1994/01/03 19:31:49 ericr +** Added cache parity error status register definitions +** +** Revision 1.2 1993/12/22 20:42:35 eric +** Added ptTrap, ptMisc and flag definitions +** Added PAL shadow regsiter definitions +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ +// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ +// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF< = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +// #define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + +#endif /* DC21164FROMGASSOURCES_INCLUDED */ diff --git a/system/alpha/palcode/ev5_alpha_defs.h b/system/alpha/palcode/ev5_alpha_defs.h new file mode 100644 index 000000000..33dc3c57a --- /dev/null +++ b/system/alpha/palcode/ev5_alpha_defs.h @@ -0,0 +1,323 @@ +#ifndef EV5_ALPHA_DEFS_INCLUDED +#define EV5_ALPHA_DEFS_INCLUDED 1 + +// from ev5_alpha_defs.mar from Lance's fetch directory +// Lower-caseified and $ signs removed ... pb Nov/95 + +// .MACRO _ALPHADEFS +// ALPHADEF_VER == 6 ; Flag the version number of this file. +// .ENDM +// .MACRO _PSDEF,_GBL +// _DEFINI PS,_GBL +//;+ +//; PS Layout - PS +//; Loc Size name function +//; ------ ------ ______ ----------------------------------- +//; <31:29> 3 SA stack alignment +//; <31:13> 24 RES Reserved MBZ +//; <12:8> 5 IPL Priority level +//; <7> 1 VMM Virtual Mach Monitor +//; <6:5> 2 RES Reserved MBZ +//; <4:3> 2 CM Current Mode +//; <2> 1 IP Interrupt Pending +//; <1:0> 2 SW Software bits +//;- + +#define ps_v_sw 0 +#define ps_m_sw (3< 32 PFN Page Frame Number +//; <31:16> 16 SOFT Bits reserved for software use +//; <15> 1 UWE User write enable +//; <14> 1 SWE Super write enable +//; <13> 1 EWE Exec write enable +//; <12> 1 KWE Kernel write enable +//; <11> 1 URE User read enable +//; <10> 1 SRE Super read enable +//; <9> 1 ERE Exec read enable +//; <8> 1 KRE Kernel read enable +//; <7:6> 2 RES Reserved SBZ +//; <5> 1 HPF Huge Page Flag +//; <4> 1 ASM Wild card address space number match +//; <3> 1 FOE Fault On execute +//; <2> 1 FOW Fault On Write +//; <1> 1 FOR Fault On Read +//; <0> 1 V valid bit +//;- +// .MACRO _PTEDEF,_GBL +// _DEFINI PTE,_GBL + +#define pte_v_pfn 32 +#define pte_m_soft (0xFFFF0000) +#define pte_v_soft 16 +#define pte_m_uwe (0x8000) +#define pte_v_uwe 15 +#define pte_m_swe (0x4000) +#define pte_v_swe 14 +#define pte_m_ewe (0x2000) +#define pte_v_ewe 13 +#define pte_m_kwe (0x1000) +#define pte_v_kwe 12 +#define pte_m_ure (0x0800) +#define pte_v_ure 11 +#define pte_m_sre (0x0400) +#define pte_v_sre 10 +#define pte_m_ere (0x0200) +#define pte_v_ere 9 +#define pte_m_kre (0x0100) +#define pte_v_kre 8 +#define pte_m_hpf (0x0020) +#define pte_v_hpf 5 +#define pte_m_asm (0x0010) +#define pte_v_asm 4 +#define pte_m_foe (0x0008) +#define pte_v_foe 3 +#define pte_m_fow (0x0004) +#define pte_v_fow 2 +#define pte_m_for (0x0002) +#define pte_v_for 1 +#define pte_m_v (0x0001) +#define pte_v_v 0 + +// _DEFEND PTE,_GBL,DEF +// .ENDM +//;+ +//; VA layout - symbol prefix VA_ +//; +//; Loc Size name function +//; ------ ------ ------- ----------------------------------- +//; <42:33> 10 SEG1 First seg table offset for mapping +//; <32:23> 10 SEG2 Second seg table offset for mapping +//; <22:13> 10 SEG3 Third seg table offset for mapping +//; <12:0> 13 OFFSET Byte within page +//;- +// .MACRO _VADEF,_GBL +// _DEFINI VA,_GBL + +#define va_m_offset (0x000000001FFF) +#define va_v_offset 0 +#define va_m_seg3 (0x0000007FE000) +#define va_v_seg3 13 +#define va_m_seg2 (0x0001FF800000) +#define va_v_seg2 23 +#define va_m_seg1 (0x7FE00000000) +#define va_v_seg1 33 + +// _DEFEND VA,_GBL,DEF +// .ENDM +//;+ +//; PRIVILEGED CONTEXT BLOCK (PCB) +//;- +// .MACRO _PCBDEF,_GBL +// _DEFINI PCB,_GBL +#define pcb_q_ksp 0 +#define pcb_q_esp 8 +#define pcb_q_ssp 16 +#define pcb_q_usp 24 +#define pcb_q_ptbr 32 +#define pcb_q_asn 40 +#define pcb_q_ast 48 +#define pcb_q_fen 56 +#define pcb_q_cc 64 +#define pcb_q_unq 72 +#define pcb_q_sct 80 + +#define pcb_v_asten 0 +#define pcb_m_asten (0x0f< ; Software completion +// exs_v_inv <1> ; Ivalid operation +// exs_v_dze <2> ; Div by zero +// exs_v_fov <3> ; Floating point overflow +// exs_v_unf <4> ; Floating point underflow +// exs_v_ine <5> ; Floating point inexact +// exs_v_iov <6> ; Floating convert to integer overflow +#define exs_v_swc 0 +#define exs_v_inv 1 +#define exs_v_dze 2 +#define exs_v_fov 3 +#define exs_v_unf 4 +#define exs_v_ine 5 +#define exs_v_iov 6 + +#define exs_m_swc (1< ; machine check in progress +// mces_v_sce <1> ; system correctable error +// mces_v_pce <2> ; processor correctable error +// mces_v_dpc <3> ; disable reporting of processor correctable errors +// mces_v_dsc <4> ; disable reporting of system correctable errors +#define mces_v_mchk 0 +#define mces_v_sce 1 +#define mces_v_pce 2 +#define mces_v_dpc 3 +#define mces_v_dsc 4 + +#define mces_m_mchk (1<,..COL=<:> +// EV5$K_REVISION'..equ'34 +// In the definitions below, registers are annotated with one of the following +// symbols: +// +// RW - The register may be read and written +// RO - The register may only be read +// WO - The register may only be written +// +// For RO and WO registers, all bits and fields within the register are also +// read-only or write-only. For RW registers, each bit or field within +// the register is annotated with one of the following: +// +// RW - The bit/field may be read and written +// RO - The bit/field may be read; writes are ignored +// WO - The bit/field may be written; reads return an UNPREDICTABLE result. +// WZ - The bit/field may be written; reads return a 0 +// WC - The bit/field may be read; writes cause state to clear +// RC - The bit/field may be read, which also causes state to clear; writes are ignored +// Architecturally-defined (SRM) registers for EVMS +#define pt0 320 +#define pt1 321 +#define pt2 322 +#define pt3 323 +#define pt4 324 +#define pt5 325 +#define pt6 326 +#define pt7 327 +#define pt8 328 +#define pt9 329 +#define pt10 330 +#define pt11 331 +#define pt12 332 +#define pt13 333 +#define pt14 334 +#define pt15 335 +#define pt16 336 +#define pt17 337 +#define pt18 338 +#define pt19 339 +#define pt20 340 +#define pt21 341 +#define pt22 342 +#define pt23 343 +#define cbox_ipr_offset 16777200 +#define sc_ctl 168 +#define sc_stat 232 +#define sc_addr 392 +#define sc_addr_nm 392 +#define sc_addr_fhm 392 +#define bc_ctl 296 +#define bc_config 456 +#define ei_stat 360 +#define ei_addr 328 +#define fill_syn 104 +#define bc_tag_addr 264 +#define ld_lock 488 +#define aster 266 +#define astrr 265 +#define exc_addr 267 +#define exc_sum 268 +#define exc_mask 269 +#define hwint_clr 277 +#define ic_flush_ctl 281 +#define icperr_stat 282 +#define ic_perr_stat 282 +#define ic_row_map 283 +#define icsr 280 +#define ifault_va_form 274 +#define intid 273 +#define ipl 272 +#define isr 256 +#define itb_is 263 +#define itb_asn 259 +#define itb_ia 261 +#define itb_iap 262 +#define itb_pte 258 +#define itb_pte_temp 260 +#define itb_tag 257 +#define ivptbr 275 +#define pal_base 270 +#define pmctr 284 +// this is not the register ps .. pb #define ps 271 +#define sirr 264 +#define sl_txmit 278 +#define sl_rcv 279 +#define alt_mode 524 +#define cc 525 +#define cc_ctl 526 +#define dc_flush 528 +#define dcperr_stat 530 +#define dc_test_ctl 531 +#define dc_test_tag 532 +#define dc_test_tag_temp 533 +#define dtb_asn 512 +#define dtb_cm 513 +#define dtb_ia 522 +#define dtb_iap 521 +#define dtb_is 523 +#define dtb_pte 515 +#define dtb_pte_temp 516 +#define dtb_tag 514 +#define mcsr 527 +#define dc_mode 534 +#define maf_mode 535 +#define mm_stat 517 +#define mvptbr 520 +#define va 518 +#define va_form 519 +#define ev5_srm__ps 0 +#define ev5_srm__pc 0 +#define ev5_srm__asten 0 +#define ev5_srm__astsr 0 +#define ev5_srm__ipir 0 +#define ev5_srm__ipl 0 +#define ev5_srm__mces 0 +#define ev5_srm__pcbb 0 +#define ev5_srm__prbr 0 +#define ev5_srm__ptbr 0 +#define ev5_srm__scbb 0 +#define ev5_srm__sirr 0 +#define ev5_srm__sisr 0 +#define ev5_srm__tbchk 0 +#define ev5_srm__tb1a 0 +#define ev5_srm__tb1ap 0 +#define ev5_srm__tb1ad 0 +#define ev5_srm__tb1ai 0 +#define ev5_srm__tbis 0 +#define ev5_srm__ksp 0 +#define ev5_srm__esp 0 +#define ev5_srm__ssp 0 +#define ev5_srm__usp 0 +#define ev5_srm__vptb 0 +#define ev5_srm__whami 0 +#define ev5_srm__cc 0 +#define ev5_srm__unq 0 +// processor-specific iprs. +#define ev5__sc_ctl 168 +#define ev5__sc_stat 232 +#define ev5__sc_addr 392 +#define ev5__bc_ctl 296 +#define ev5__bc_config 456 +#define bc_config_k_size_1mb 1 +#define bc_config_k_size_2mb 2 +#define bc_config_k_size_4mb 3 +#define bc_config_k_size_8mb 4 +#define bc_config_k_size_16mb 5 +#define bc_config_k_size_32mb 6 +#define bc_config_k_size_64mb 7 +#define ev5__ei_stat 360 +#define ev5__ei_addr 328 +#define ev5__fill_syn 104 +#define ev5__bc_tag_addr 264 +#define ev5__aster 266 +#define ev5__astrr 265 +#define ev5__exc_addr 267 +#define exc_addr_v_pa 2 +#define exc_addr_s_pa 62 +#define ev5__exc_sum 268 +#define ev5__exc_mask 269 +#define ev5__hwint_clr 277 +#define ev5__ic_flush_ctl 281 +#define ev5__icperr_stat 282 +#define ev5__ic_perr_stat 282 +#define ev5__ic_row_map 283 +#define ev5__icsr 280 +#define ev5__ifault_va_form 274 +#define ev5__ifault_va_form_nt 274 +#define ifault_va_form_nt_v_vptb 30 +#define ifault_va_form_nt_s_vptb 34 +#define ev5__intid 273 +#define ev5__ipl 272 +#define ev5__itb_is 263 +#define ev5__itb_asn 259 +#define ev5__itb_ia 261 +#define ev5__itb_iap 262 +#define ev5__itb_pte 258 +#define ev5__itb_pte_temp 260 +#define ev5__itb_tag 257 +#define ev5__ivptbr 275 +#define ivptbr_v_vptb 30 +#define ivptbr_s_vptb 34 +#define ev5__pal_base 270 +#define ev5__pmctr 284 +#define ev5__ps 271 +#define ev5__isr 256 +#define ev5__sirr 264 +#define ev5__sl_txmit 278 +#define ev5__sl_rcv 279 +#define ev5__alt_mode 524 +#define ev5__cc 525 +#define ev5__cc_ctl 526 +#define ev5__dc_flush 528 +#define ev5__dcperr_stat 530 +#define ev5__dc_test_ctl 531 +#define ev5__dc_test_tag 532 +#define ev5__dc_test_tag_temp 533 +#define ev5__dtb_asn 512 +#define ev5__dtb_cm 513 +#define ev5__dtb_ia 522 +#define ev5__dtb_iap 521 +#define ev5__dtb_is 523 +#define ev5__dtb_pte 515 +#define ev5__dtb_pte_temp 516 +#define ev5__dtb_tag 514 +#define ev5__mcsr 527 +#define ev5__dc_mode 534 +#define ev5__maf_mode 535 +#define ev5__mm_stat 517 +#define ev5__mvptbr 520 +#define ev5__va 518 +#define ev5__va_form 519 +#define ev5__va_form_nt 519 +#define va_form_nt_s_va 19 +#define va_form_nt_v_vptb 30 +#define va_form_nt_s_vptb 34 +#define ev5s_ev5_def 10 +#define ev5_def 0 +// cbox registers. +#define sc_ctl_v_sc_fhit 0 +#define sc_ctl_v_sc_flush 1 +#define sc_ctl_s_sc_tag_stat 6 +#define sc_ctl_v_sc_tag_stat 2 +#define sc_ctl_s_sc_fb_dp 4 +#define sc_ctl_v_sc_fb_dp 8 +#define sc_ctl_v_sc_blk_size 12 +#define sc_ctl_s_sc_set_en 3 +#define sc_ctl_v_sc_set_en 13 +#define sc_ctl_s_sc_soft_repair 3 +#define sc_ctl_v_sc_soft_repair 16 +#define sc_stat_s_sc_tperr 3 +#define sc_stat_v_sc_tperr 0 +#define sc_stat_s_sc_dperr 8 +#define sc_stat_v_sc_dperr 3 +#define sc_stat_s_cbox_cmd 5 +#define sc_stat_v_cbox_cmd 11 +#define sc_stat_v_sc_scnd_err 16 +#define sc_addr_fhm_v_sc_tag_parity 4 +#define sc_addr_fhm_s_tag_stat_sb0 3 +#define sc_addr_fhm_v_tag_stat_sb0 5 +#define sc_addr_fhm_s_tag_stat_sb1 3 +#define sc_addr_fhm_v_tag_stat_sb1 8 +#define sc_addr_fhm_s_ow_mod0 2 +#define sc_addr_fhm_v_ow_mod0 11 +#define sc_addr_fhm_s_ow_mod1 2 +#define sc_addr_fhm_v_ow_mod1 13 +#define sc_addr_fhm_s_tag_lo 17 +#define sc_addr_fhm_v_tag_lo 15 +#define sc_addr_fhm_s_tag_hi 7 +#define sc_addr_fhm_v_tag_hi 32 +#define bc_ctl_v_bc_enabled 0 +#define bc_ctl_v_alloc_cyc 1 +#define bc_ctl_v_ei_opt_cmd 2 +#define bc_ctl_v_ei_opt_cmd_mb 3 +#define bc_ctl_v_corr_fill_dat 4 +#define bc_ctl_v_vtm_first 5 +#define bc_ctl_v_ei_ecc_or_parity 6 +#define bc_ctl_v_bc_fhit 7 +#define bc_ctl_s_bc_tag_stat 5 +#define bc_ctl_v_bc_tag_stat 8 +#define bc_ctl_s_bc_bad_dat 2 +#define bc_ctl_v_bc_bad_dat 13 +#define bc_ctl_v_ei_dis_err 15 +#define bc_ctl_v_tl_pipe_latch 16 +#define bc_ctl_s_bc_wave_pipe 2 +#define bc_ctl_v_bc_wave_pipe 17 +#define bc_ctl_s_pm_mux_sel 6 +#define bc_ctl_v_pm_mux_sel 19 +#define bc_ctl_v_dbg_mux_sel 25 +#define bc_ctl_v_dis_baf_byp 26 +#define bc_ctl_v_dis_sc_vic_buf 27 +#define bc_ctl_v_dis_sys_addr_par 28 +#define bc_ctl_v_read_dirty_cln_shr 29 +#define bc_ctl_v_write_read_bubble 30 +#define bc_ctl_v_bc_wave_pipe_2 31 +#define bc_ctl_v_auto_dack 32 +#define bc_ctl_v_dis_byte_word 33 +#define bc_ctl_v_stclk_delay 34 +#define bc_ctl_v_write_under_miss 35 +#define bc_config_s_bc_size 3 +#define bc_config_v_bc_size 0 +#define bc_config_s_bc_rd_spd 4 +#define bc_config_v_bc_rd_spd 4 +#define bc_config_s_bc_wr_spd 4 +#define bc_config_v_bc_wr_spd 8 +#define bc_config_s_bc_rd_wr_spc 3 +#define bc_config_v_bc_rd_wr_spc 12 +#define bc_config_s_fill_we_offset 3 +#define bc_config_v_fill_we_offset 16 +#define bc_config_s_bc_we_ctl 9 +#define bc_config_v_bc_we_ctl 20 +// cbox registers, continued +#define ei_stat_s_sys_id 4 +#define ei_stat_v_sys_id 24 +#define ei_stat_v_bc_tperr 28 +#define ei_stat_v_bc_tc_perr 29 +#define ei_stat_v_ei_es 30 +#define ei_stat_v_cor_ecc_err 31 +#define ei_stat_v_unc_ecc_err 32 +#define ei_stat_v_ei_par_err 33 +#define ei_stat_v_fil_ird 34 +#define ei_stat_v_seo_hrd_err 35 +// +#define bc_tag_addr_v_hit 12 +#define bc_tag_addr_v_tagctl_p 13 +#define bc_tag_addr_v_tagctl_d 14 +#define bc_tag_addr_v_tagctl_s 15 +#define bc_tag_addr_v_tagctl_v 16 +#define bc_tag_addr_v_tag_p 17 +#define bc_tag_addr_s_bc_tag 19 +#define bc_tag_addr_v_bc_tag 20 +// ibox and icache registers. +#define aster_v_kar 0 +#define aster_v_ear 1 +#define aster_v_sar 2 +#define aster_v_uar 3 +#define astrr_v_kar 0 +#define astrr_v_ear 1 +#define astrr_v_sar 2 +#define astrr_v_uar 3 +#define exc_addr_v_pal 0 +#define exc_sum_v_swc 10 +#define exc_sum_v_inv 11 +#define exc_sum_v_dze 12 +#define exc_sum_v_fov 13 +#define exc_sum_v_unf 14 +#define exc_sum_v_ine 15 +#define exc_sum_v_iov 16 +#define hwint_clr_v_pc0c 27 +#define hwint_clr_v_pc1c 28 +#define hwint_clr_v_pc2c 29 +#define hwint_clr_v_crdc 32 +#define hwint_clr_v_slc 33 +// ibox and icache registers, continued +#define icperr_stat_v_dpe 11 +#define icperr_stat_v_tpe 12 +#define icperr_stat_v_tmr 13 +#define ic_perr_stat_v_dpe 11 +#define ic_perr_stat_v_tpe 12 +#define ic_perr_stat_v_tmr 13 +#define icsr_v_pma 8 +#define icsr_v_pmp 9 +#define icsr_v_byt 17 +#define icsr_v_fmp 18 +#define icsr_v_im0 20 +#define icsr_v_im1 21 +#define icsr_v_im2 22 +#define icsr_v_im3 23 +#define icsr_v_tmm 24 +#define icsr_v_tmd 25 +#define icsr_v_fpe 26 +#define icsr_v_hwe 27 +#define icsr_s_spe 2 +#define icsr_v_spe 28 +#define icsr_v_sde 30 +#define icsr_v_crde 32 +#define icsr_v_sle 33 +#define icsr_v_fms 34 +#define icsr_v_fbt 35 +#define icsr_v_fbd 36 +#define icsr_v_dbs 37 +#define icsr_v_ista 38 +#define icsr_v_tst 39 +#define ifault_va_form_s_va 30 +#define ifault_va_form_v_va 3 +#define ifault_va_form_s_vptb 31 +#define ifault_va_form_v_vptb 33 +#define ifault_va_form_nt_s_va 19 +#define ifault_va_form_nt_v_va 3 +#define intid_s_intid 5 +#define intid_v_intid 0 +// ibox and icache registers, continued +#define ipl_s_ipl 5 +#define ipl_v_ipl 0 +#define itb_is_s_va 30 +#define itb_is_v_va 13 +#define itb_asn_s_asn 7 +#define itb_asn_v_asn 4 +#define itb_pte_v_asm 4 +#define itb_pte_s_gh 2 +#define itb_pte_v_gh 5 +#define itb_pte_v_kre 8 +#define itb_pte_v_ere 9 +#define itb_pte_v_sre 10 +#define itb_pte_v_ure 11 +#define itb_pte_s_pfn 27 +#define itb_pte_v_pfn 32 +#define itb_pte_temp_v_asm 13 +#define itb_pte_temp_v_kre 18 +#define itb_pte_temp_v_ere 19 +#define itb_pte_temp_v_sre 20 +#define itb_pte_temp_v_ure 21 +#define itb_pte_temp_s_gh 3 +#define itb_pte_temp_v_gh 29 +#define itb_pte_temp_s_pfn 27 +#define itb_pte_temp_v_pfn 32 +// ibox and icache registers, continued +#define itb_tag_s_va 30 +#define itb_tag_v_va 13 +#define pal_base_s_pal_base 26 +#define pal_base_v_pal_base 14 +#define pmctr_s_sel2 4 +#define pmctr_v_sel2 0 +#define pmctr_s_sel1 4 +#define pmctr_v_sel1 4 +#define pmctr_v_killk 8 +#define pmctr_v_killp 9 +#define pmctr_s_ctl2 2 +#define pmctr_v_ctl2 10 +#define pmctr_s_ctl1 2 +#define pmctr_v_ctl1 12 +#define pmctr_s_ctl0 2 +#define pmctr_v_ctl0 14 +#define pmctr_s_ctr2 14 +#define pmctr_v_ctr2 16 +#define pmctr_v_killu 30 +#define pmctr_v_sel0 31 +#define pmctr_s_ctr1 16 +#define pmctr_v_ctr1 32 +#define pmctr_s_ctr0 16 +#define pmctr_v_ctr0 48 +#define ps_v_cm0 3 +#define ps_v_cm1 4 +#define isr_s_astrr 4 +#define isr_v_astrr 0 +#define isr_s_sisr 15 +#define isr_v_sisr 4 +#define isr_v_atr 19 +#define isr_v_i20 20 +#define isr_v_i21 21 +#define isr_v_i22 22 +#define isr_v_i23 23 +#define isr_v_pc0 27 +#define isr_v_pc1 28 +#define isr_v_pc2 29 +#define isr_v_pfl 30 +#define isr_v_mck 31 +#define isr_v_crd 32 +#define isr_v_sli 33 +#define isr_v_hlt 34 +#define sirr_s_sirr 15 +#define sirr_v_sirr 4 +// ibox and icache registers, continued +#define sl_txmit_v_tmt 7 +#define sl_rcv_v_rcv 6 +// mbox and dcache registers. +#define alt_mode_v_am0 3 +#define alt_mode_v_am1 4 +#define cc_ctl_v_cc_ena 32 +#define dcperr_stat_v_seo 0 +#define dcperr_stat_v_lock 1 +#define dcperr_stat_v_dp0 2 +#define dcperr_stat_v_dp1 3 +#define dcperr_stat_v_tp0 4 +#define dcperr_stat_v_tp1 5 +// the following two registers are used exclusively for test and diagnostics. +// they should not be referenced in normal operation. +#define dc_test_ctl_v_bank0 0 +#define dc_test_ctl_v_bank1 1 +#define dc_test_ctl_v_fill_0 2 +#define dc_test_ctl_s_index 10 +#define dc_test_ctl_v_index 3 +#define dc_test_ctl_s_fill_1 19 +#define dc_test_ctl_v_fill_1 13 +#define dc_test_ctl_s_fill_2 32 +#define dc_test_ctl_v_fill_2 32 +// mbox and dcache registers, continued. +#define dc_test_tag_v_tag_par 2 +#define dc_test_tag_v_ow0 11 +#define dc_test_tag_v_ow1 12 +#define dc_test_tag_s_tag 26 +#define dc_test_tag_v_tag 13 +#define dc_test_tag_temp_v_tag_par 2 +#define dc_test_tag_temp_v_d0p0 3 +#define dc_test_tag_temp_v_d0p1 4 +#define dc_test_tag_temp_v_d1p0 5 +#define dc_test_tag_temp_v_d1p1 6 +#define dc_test_tag_temp_v_ow0 11 +#define dc_test_tag_temp_v_ow1 12 +#define dc_test_tag_temp_s_tag 26 +#define dc_test_tag_temp_v_tag 13 +#define dtb_asn_s_asn 7 +#define dtb_asn_v_asn 57 +#define dtb_cm_v_cm0 3 +#define dtb_cm_v_cm1 4 +#define dtbis_s_va0 30 +#define dtbis_v_va0 13 +#define dtb_pte_v_for 1 +#define dtb_pte_v_fow 2 +#define dtb_pte_v_asm 4 +#define dtb_pte_s_gh 2 +#define dtb_pte_v_gh 5 +#define dtb_pte_v_kre 8 +#define dtb_pte_v_ere 9 +#define dtb_pte_v_sre 10 +#define dtb_pte_v_ure 11 +#define dtb_pte_v_kwe 12 +#define dtb_pte_v_ewe 13 +#define dtb_pte_v_swe 14 +#define dtb_pte_v_uwe 15 +#define dtb_pte_s_pfn 27 +#define dtb_pte_v_pfn 32 +// mbox and dcache registers, continued. +#define dtb_pte_temp_v_for 0 +#define dtb_pte_temp_v_fow 1 +#define dtb_pte_temp_v_kre 2 +#define dtb_pte_temp_v_ere 3 +#define dtb_pte_temp_v_sre 4 +#define dtb_pte_temp_v_ure 5 +#define dtb_pte_temp_v_kwe 6 +#define dtb_pte_temp_v_ewe 7 +#define dtb_pte_temp_v_swe 8 +#define dtb_pte_temp_v_uwe 9 +#define dtb_pte_temp_v_asm 10 +#define dtb_pte_temp_s_fill_0 2 +#define dtb_pte_temp_v_fill_0 11 +#define dtb_pte_temp_s_pfn 27 +#define dtb_pte_temp_v_pfn 13 +#define dtb_tag_s_va 30 +#define dtb_tag_v_va 13 +// most mcsr bits are used for testability and diagnostics only. +// for normal operation, they will be supported in the following configuration: +// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, +// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 +#define mcsr_v_big_endian 0 +#define mcsr_v_sp0 1 +#define mcsr_v_sp1 2 +#define mcsr_v_mbox_sel 3 +#define mcsr_v_e_big_endian 4 +#define mcsr_v_dbg_packet_sel 5 +#define dc_mode_v_dc_ena 0 +#define dc_mode_v_dc_fhit 1 +#define dc_mode_v_dc_bad_parity 2 +#define dc_mode_v_dc_perr_dis 3 +#define dc_mode_v_dc_doa 4 +#define maf_mode_v_maf_nomerge 0 +#define maf_mode_v_wb_flush_always 1 +#define maf_mode_v_wb_nomerge 2 +#define maf_mode_v_io_nomerge 3 +#define maf_mode_v_wb_cnt_disable 4 +#define maf_mode_v_maf_arb_disable 5 +#define maf_mode_v_dread_pending 6 +#define maf_mode_v_wb_pending 7 +// mbox and dcache registers, continued. +#define mm_stat_v_wr 0 +#define mm_stat_v_acv 1 +#define mm_stat_v_for 2 +#define mm_stat_v_fow 3 +#define mm_stat_v_dtb_miss 4 +#define mm_stat_v_bad_va 5 +#define mm_stat_s_ra 5 +#define mm_stat_v_ra 6 +#define mm_stat_s_opcode 6 +#define mm_stat_v_opcode 11 +#define mvptbr_s_vptb 31 +#define mvptbr_v_vptb 33 +#define va_form_s_va 30 +#define va_form_v_va 3 +#define va_form_s_vptb 31 +#define va_form_v_vptb 33 +#define va_form_nt_s_va 19 +#define va_form_nt_v_va 3 +//.endm + +#endif diff --git a/system/alpha/palcode/ev5_impure.h b/system/alpha/palcode/ev5_impure.h new file mode 100644 index 000000000..84d700c32 --- /dev/null +++ b/system/alpha/palcode/ev5_impure.h @@ -0,0 +1,392 @@ +#ifndef EV5_IMPURE_INCLUDED +#define EV5_IMPURE_INCLUDED + +/* +// This uses the Hudson file format from "impure.h" but with the fields from +// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 + +//orig file: impure.sdl +//orig +//orig Abstract: PAL impure scratch area and logout area data structure definitions for +//orig Alpha firmware. +//orig +//orig +//orig module $pal_impure; +//orig +//orig Edit Date Who Description +//orig ---- --------- --- --------------------- +//orig 1 7-Jul-93 JEM Initial Entry +//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area +//orig Delete mvptbr +//orig Calculate pal$logout from end of impure area +//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions +//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl; +//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl, +//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock +//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4 +//orig add cns$ipr_offset +//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. +//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame +//orig +//orig +//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file +//orig + +** Macros for saving/restoring data to/from the PAL impure scratch +** area. +** +** The console save state area is larger than the addressibility +** of the HW_LD/ST instructions (10-bit signed byte displacement), +** so some adjustments to the base offsets, as well as the offsets +** within each base region, are necessary. +** +** The console save state area is divided into two segments; the +** CPU-specific segment and the platform-specific segment. The +** state that is saved in the CPU-specific segment includes GPRs, +** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved +** in the platform-specific segment. +** +** The impure pointer will need to be adjusted by a different offset +** value for each region within a given segment. The SAVE and RESTORE +** macros will auto-magically adjust the offsets accordingly. +** +*/ + +#define SAVE_GPR(reg,offset,base) \ + stq_p reg, ((offset-0x200)&0x3FF)(base) + +#define RESTORE_GPR(reg,offset,base) \ + ldq_p reg, ((offset-0x200)&0x3FF)(base) + + +#define SAVE_FPR(reg,offset,base) \ + stt reg, ((offset-0x200)&0x3FF)(base) + +#define RESTORE_FPR(reg,offset,base) \ + ldt reg, ((offset-0x200)&0x3FF)(base) + +#define SAVE_IPR(reg,offset,base) \ + mfpr v0, reg; \ + stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base) + +#define RESTORE_IPR(reg,offset,base) \ + ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \ + mtpr v0, reg + +#define SAVE_SHADOW(reg,offset,base) \ + stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) + +#define RESTORE_SHADOW(reg,offset,base)\ + ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base) + +/* orig Structure of the processor-specific impure area */ + +/* orig aggregate impure struct prefix "" tag ""; + * orig cns$flag quadword; + * orig cns$hlt quadword; +*/ + +/* Define base for debug monitor compatibility */ +#define CNS_Q_BASE 0x000 +#define CNS_Q_FLAG 0x100 +#define CNS_Q_HALT 0x108 + + +/* orig constant ( + * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, + * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, + * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, + * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$gpr quadword dimension 32; +*/ +/* Offset to base of saved GPR area - 32 quadword */ +#define CNS_Q_GPR 0x110 +#define cns_gpr CNS_Q_GPR + +/* orig constant ( + * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, + * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, + * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, + * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$fpr quadword dimension 32; +*/ +/* Offset to base of saved FPR area - 32 quadwords */ +#define CNS_Q_FPR 0x210 + +/* orig #t=.; + * orig cns$mchkflag quadword; +*/ +#define CNS_Q_MCHK 0x310 + +/* orig constant cns$pt_offset equals .; + * orig constant ( + * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, + * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, + * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, + * orig cns$pt21,cns$pt22,cns$pt23 + * orig ) equals . increment 8 prefix "" tag ""; + * orig cns$pt quadword dimension 24; +*/ +/* Offset to base of saved PALtemp area - 25 quadwords */ +#define CNS_Q_PT 0x318 + +/* orig cns$shadow8 quadword; + * orig cns$shadow9 quadword; + * orig cns$shadow10 quadword; + * orig cns$shadow11 quadword; + * orig cns$shadow12 quadword; + * orig cns$shadow13 quadword; + * orig cns$shadow14 quadword; + * orig cns$shadow25 quadword; +*/ +/* Offset to base of saved PALshadow area - 8 quadwords */ +#define CNS_Q_SHADOW 0x3D8 + +/* Offset to base of saved IPR area */ +#define CNS_Q_IPR 0x418 + +/* orig constant cns$ipr_offset equals .; */ +/* orig cns$exc_addr quadword; */ +#define CNS_Q_EXC_ADDR 0x418 +/* orig cns$pal_base quadword; */ +#define CNS_Q_PAL_BASE 0x420 +/* orig cns$mm_stat quadword; */ +#define CNS_Q_MM_STAT 0x428 +/* orig cns$va quadword; */ +#define CNS_Q_VA 0x430 +/* orig cns$icsr quadword; */ +#define CNS_Q_ICSR 0x438 +/* orig cns$ipl quadword; */ +#define CNS_Q_IPL 0x440 +/* orig cns$ps quadword; // Ibox current mode */ +#define CNS_Q_IPS 0x448 +/* orig cns$itb_asn quadword; */ +#define CNS_Q_ITB_ASN 0x450 +/* orig cns$aster quadword; */ +#define CNS_Q_ASTER 0x458 +/* orig cns$astrr quadword; */ +#define CNS_Q_ASTRR 0x460 +/* orig cns$isr quadword; */ +#define CNS_Q_ISR 0x468 +/* orig cns$ivptbr quadword; */ +#define CNS_Q_IVPTBR 0x470 +/* orig cns$mcsr quadword; */ +#define CNS_Q_MCSR 0x478 +/* orig cns$dc_mode quadword; */ +#define CNS_Q_DC_MODE 0x480 +/* orig cns$maf_mode quadword; */ +#define CNS_Q_MAF_MODE 0x488 +/* orig cns$sirr quadword; */ +#define CNS_Q_SIRR 0x490 +/* orig cns$fpcsr quadword; */ +#define CNS_Q_FPCSR 0x498 +/* orig cns$icperr_stat quadword; */ +#define CNS_Q_ICPERR_STAT 0x4A0 +/* orig cns$pmctr quadword; */ +#define CNS_Q_PM_CTR 0x4A8 +/* orig cns$exc_sum quadword; */ +#define CNS_Q_EXC_SUM 0x4B0 +/* orig cns$exc_mask quadword; */ +#define CNS_Q_EXC_MASK 0x4B8 +/* orig cns$intid quadword; */ +#define CNS_Q_INT_ID 0x4C0 +/* orig cns$dcperr_stat quadword; */ +#define CNS_Q_DCPERR_STAT 0x4C8 +/* orig cns$sc_stat quadword; */ +#define CNS_Q_SC_STAT 0x4D0 +/* orig cns$sc_addr quadword; */ +#define CNS_Q_SC_ADDR 0x4D8 +/* orig cns$sc_ctl quadword; */ +#define CNS_Q_SC_CTL 0x4E0 +/* orig cns$bc_tag_addr quadword; */ +#define CNS_Q_BC_TAG_ADDR 0x4E8 +/* orig cns$ei_stat quadword; */ +#define CNS_Q_EI_STAT 0x4F0 +/* orig cns$ei_addr quadword; */ +#define CNS_Q_EI_ADDR 0x4F8 +/* orig cns$fill_syn quadword; */ +#define CNS_Q_FILL_SYN 0x500 +/* orig cns$ld_lock quadword; */ +#define CNS_Q_LD_LOCK 0x508 +/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */ +#define CNS_Q_BC_CTL 0x510 +/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ +#define CNS_Q_PM_CTL 0x518 +/* orig cns$bc_config quadword; // shadow of on chip bc_config */ +#define CNS_Q_BC_CFG 0x520 + +/* orig constant cns$size equals .; + * orig + * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8; + * orig constant pal$impure_specific_size equals (.+7) & %xfff8; + * orig constant cns$mchksize equals (.+7-#t) & %xfff8; + * orig constant pal$logout_area equals pal$impure_specific_size ; + * orig end impure; +*/ + +/* This next set of stuff came from the old code ..pb */ +#define CNS_Q_SROM_REV 0x528 +#define CNS_Q_PROC_ID 0x530 +#define CNS_Q_MEM_SIZE 0x538 +#define CNS_Q_CYCLE_CNT 0x540 +#define CNS_Q_SIGNATURE 0x548 +#define CNS_Q_PROC_MASK 0x550 +#define CNS_Q_SYSCTX 0x558 + + + +#define MACHINE_CHECK_CRD_BASE 0 +#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) + + + +/* orig + * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; + * orig SPROCESS bitfield length 1 ; + * orig FILL_0 bitfield length 3 fill tag $$; + * orig FRQ2 bitfield length 2 ; + * orig FRQ1 bitfield length 2 ; + * orig FRQ0 bitfield length 2 ; + * orig CTL2 bitfield length 2 ; + * orig CTL1 bitfield length 2 ; + * orig CTL0 bitfield length 2 ; + * orig FILL_1 bitfield length 16 fill tag $$; + * orig FILL_2 bitfield length 32 fill tag $$; + * orig end EV5PMCTRCTL_BITS; + * orig + * orig end_module $pal_impure; + * orig + * orig module $pal_logout; + * orig + * orig // + * orig // Start definition of Corrected Error Frame + * orig // + */ + +/* + * orig aggregate crd_logout struct prefix "" tag ""; + */ + +#ifdef SIMOS +#define pal_logout_area 0x600 +#define mchk_crd_base 0 +#endif + +/* orig mchk$crd_flag quadword; */ +#define mchk_crd_flag 0 +/* orig mchk$crd_offsets quadword; */ +#define mchk_crd_offsets 8 +/* orig + * orig // Pal-specific information */ +#define mchk_crd_mchk_code 0x10 +/* orig mchk$crd_mchk_code quadword; + * orig + * orig // CPU-specific information + * orig constant mchk$crd_cpu_base equals . ; + * orig mchk$crd_ei_addr quadword; */ +#define mchk_crd_ei_addr 0x18 +/* orig mchk$crd_fill_syn quadword; */ +#define mchk_crd_fill_syn 0x20 +/* orig mchk$crd_ei_stat quadword; */ +#define mchk_crd_ei_stat 0x28 +/* orig mchk$crd_isr quadword; */ +#define mchk_crd_isr 0x30 + +/* + * Hacked up constants for the turbolaser build. Hope + * this is moreless correct + */ + +#define mchk_crd_whami 0x38 +#define mchk_crd_tldev 0x40 +#define mchk_crd_tlber 0x48 +#define mchk_crd_tlesr0 0x50 +#define mchk_crd_tlesr1 0x58 +#define mchk_crd_tlesr2 0x60 +#define mchk_crd_tlesr3 0x68 +#define mchk_crd_rsvd 0x70 + + +#ifdef SIMOS +/* + * mchk area seems different for tlaser + */ + +#define mchk_crd_size 0x80 +#define mchk_mchk_base (mchk_crd_size) + +#define mchk_tlber 0x0 +#define mchk_tlepaerr 0x8 +#define mchk_tlepderr 0x10 +#define mchk_tlepmerr 0x18 + + +#endif + + +/* orig + * orig // System-specific information + * orig constant mchk$crd_sys_base equals . ; + * orig constant mchk$crd_size equals (.+7) & %xfff8; + * orig + * orig end crd_logout; + * orig // + * orig // Start definition of Machine check logout Frame + * orig // + * orig aggregate logout struct prefix "" tag ""; + * orig mchk$flag quadword; */ +/* orig mchk$offsets quadword; */ +/* orig + * orig // Pal-specific information + * orig mchk$mchk_code quadword; */ +/* + + * orig mchk$pt quadword dimension 24; + * orig + * orig // CPU-specific information + * orig constant mchk$cpu_base equals . ; + * orig mchk$exc_addr quadword; + * orig mchk$exc_sum quadword; + * orig mchk$exc_mask quadword; + * orig mchk$pal_base quadword; + * orig mchk$isr quadword; + * orig mchk$icsr quadword; + * orig mchk$ic_perr_stat quadword; + * orig mchk$dc_perr_stat quadword; + * orig mchk$va quadword; + * orig mchk$mm_stat quadword; + * orig mchk$sc_addr quadword; + * orig mchk$sc_stat quadword; + * orig mchk$bc_tag_addr quadword; + * orig mchk$ei_addr quadword; + * orig mchk$fill_syn quadword; + * orig mchk$ei_stat quadword; + * orig mchk$ld_lock quadword; + * orig + * orig // System-specific information + * orig + * orig constant mchk$sys_base equals . ; + * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff + * orig + * orig constant mchk$size equals (.+7) & %xfff8; + * orig + * orig + * orig constant mchk$crd_base equals 0 ; + * orig constant mchk$mchk_base equals mchk$crd_size ; + * orig + * orig + * orig end logout; + * orig + * orig end_module $pal_logout; +*/ + + + + +/* this is lingering in the old ladbx code but looks like it was from ev4 days. + * This was 0x160 in the old days..pb +*/ +#define LAF_K_SIZE MACHINE_CHECK_SIZE +#endif diff --git a/system/alpha/palcode/ev5_osfalpha_defs.h b/system/alpha/palcode/ev5_osfalpha_defs.h new file mode 100644 index 000000000..08a110075 --- /dev/null +++ b/system/alpha/palcode/ev5_osfalpha_defs.h @@ -0,0 +1,160 @@ +#ifndef EV5_OSFALPHA_DEFS_INCLUDED +#define EV5_OSFALPHA_DEFS_INCLUDED 1 + + +// from ev5_osfalpha_defs.mar from Lance's fetch directory +// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95 + +//orig .MACRO $OSF_ALPHADEFS +//orig OSF_ALPHADEF_VER == 5 ; Flag the version number of this file. +//orig .ENDM +//orig .MACRO $OSF_PSDEF,$GBL +//orig $DEFINI OSFPS,$GBL +//orig;+ +//orig; PS Layout - PS +//orig; Loc Size name function +//orig; ------ ------ ----- ----------------------------------- +//orig; <0:2> 3 IPL Prio level +//orig; <3> 1 CM Current Mode +//orig;- + +#define osfps_v_mode 3 +#define osfps_m_mode (1< 32 PFN Page Frame Number +//orig; <31:16> 16 SOFT Bits reserved for software use +//orig; <15:14> 2 +//orig; <13> 1 UWE User write enable +//orig; <12> 1 KWE Kernel write enable +//orig; <11:10> 2 +//orig; <9> 1 URE User read enable +//orig; <8> 1 KRE Kernel read enable +//orig; <7:6> 2 RES Reserved SBZ +//orig; <5> 1 HPF Huge Page Flag +//orig; <4> 1 ASM Wild card address space number match +//orig; <3> 1 FOE Fault On execute +//orig; <2> 1 FOW Fault On Write +//orig; <1> 1 FOR Fault On Read +//orig; <0> 1 V valid bit +//orig;- + +//orig .MACRO _OSF_PTEDEF,_GBL +//orig _DEFINI OSFPTE,_GBL + +#define osfpte_v_pfn 32 +#define osfpte_m_soft (0xFFFF0000) +#define osfpte_v_soft 16 +#define osfpte_m_uwe (0x2000) +#define osfpte_v_uwe 13 +#define osfpte_m_kwe (0x1000) +#define osfpte_v_kwe 12 +#define osfpte_m_ure (0x0200) +#define osfpte_v_ure 9 +#define osfpte_m_kre (0x0100) +#define osfpte_v_kre 8 +#define osfpte_m_hpf (0x0020) +#define osfpte_v_hpf 5 +#define osfpte_m_asm (0x0010) +#define osfpte_v_asm 4 +#define osfpte_m_foe (0x0008) +#define osfpte_v_foe 3 +#define osfpte_m_fow (0x0004) +#define osfpte_v_fow 2 +#define osfpte_m_for (0x0002) +#define osfpte_v_for 1 +#define osfpte_m_v (0x0001) +#define osfpte_v_v 0 + +#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm) +#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe) + +//orig _DEFEND OSFPTE,_GBL,DEF +//orig .ENDM + +//orig;+ +//orig; VA layout - symbol prefix VA_ +//orig; +//orig; Loc Size name function +//orig; ------ ------ ------- ----------------------------------- +//orig; <42:33> 10 SEG1 First seg table offset for mapping +//orig; <32:23> 10 SEG2 Second seg table offset for mapping +//orig; <22:13> 10 SEG3 Third seg table offset for mapping +//orig; <12:0> 13 OFFSET Byte within page +//orig;- +//orig .MACRO _OSF_VADEF,_GBL +//orig _DEFINI OSFVA,_GBL + +#define osfva_m_offset (0x000000001FFF) +#define osfva_v_offset 0 +#define osfva_m_seg3 (0x0000007FE000) +#define osfva_v_seg3 13 +#define osfva_m_seg2 (0x0001FF800000) +#define osfva_v_seg2 23 +#define osfva_m_seg1 (0x7FE00000000) +#define osfva_v_seg1 33 + +//orig _DEFEND OSFVA,_GBL,DEF +//orig .ENDM +//orig;+ +//orig; PRIVILEGED CONTEXT BLOCK (PCB) +//orig;- +//orig .MACRO _OSF_PCBDEF,_GBL +//orig _DEFINI OSFPCB,_GBL + +#define osfpcb_q_ksp (0x0000) +#define osfpcb_q_usp (0x0008) +#define osfpcb_q_Usp (0x0008) +#define osfpcb_q_mmptr (0x0010) +#define osfpcb_q_Mmptr (0x0010) +#define osfpcb_l_cc (0x0018) +#define osfpcb_l_asn (0x001C) +#define osfpcb_q_unique (0x0020) +#define osfpcb_q_fen (0x0028) +#define osfpcb_v_pme 62 + +//orig _DEFEND OSFPCB,_GBL,DEF +//orig .ENDM +//orig;+ +//orig; Stack Frame +//orig;- +//orig .MACRO _OSF_SFDEF,_GBL +//orig _DEFINI OSFSF,_GBL + +#define osfsf_ps (0x00) +#define osfsf_pc (0x08) +#define osfsf_gp (0x10) +#define osfsf_a0 (0x18) +#define osfsf_a1 (0x20) +#define osfsf_a2 (0x28) +#define osfsf_c_size (0x30) + +//orig _DEFEND OSFSF,_GBL,DEF +//orig .ENDM + +#endif diff --git a/system/alpha/palcode/ev5_paldef.h b/system/alpha/palcode/ev5_paldef.h new file mode 100644 index 000000000..5f9241b12 --- /dev/null +++ b/system/alpha/palcode/ev5_paldef.h @@ -0,0 +1,185 @@ +#ifndef EV5_PALDEF_INCLUDED +#define EV5_PALDEF_INCLUDED 1 + +// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95 +// some entries have been superceeded by the more recent evt_defs.h + +// These are lower-caseified and have the $ signs (unnecessarily we now discover) removed. + +// Note that at the bottom of this file is the version of ev5_defs.mar +// which is more recent than the top part of the file and contains overlapping information...pb Nov/95 + +// .MACRO PALDEFS +// PALDEF_VER == 1 ; Flag the version number of this file. +// .ENDM +// +// +// .MACRO _HALT_CODES,_GBL +// _DEFINI HALT_CODES,_GBL + +#define hlt_c_reset 0 +#define hlt_c_hw_halt 1 +#define hlt_c_ksp_inval 2 +#define hlt_c_scbb_inval 3 +#define hlt_c_ptbr_inval 4 +#define hlt_c_sw_halt 5 +#define hlt_c_dbl_mchk 6 +#define hlt_c_mchk_from_pal 7 +#define hlt_c_start 32 +#define hlt_c_callback 33 +#define hlt_c_mpstart 34 +#define hlt_c_lfu_start 35 + +// halt codes above 255 reserved for platform specific errors +// _DEFEND HALT_CODES,_GBL,DEF +// .ENDM +// .MACRO _MCHK_CODES,_GBL +// _DEFINI MCHK_CODES,_GBL + +#define mchk_c_tperr (64<<1) +#define mchk_c_tcperr (65<<1) +#define mchk_c_herr (66<<1) +#define mchk_c_ecc_c (67<<1) +#define mchk_c_ecc_nc (68<<1) +#define mchk_c_unknown (69<<1) +#define mchk_c_cacksoft (70<<1) +#define mchk_c_bugcheck (71<<1) +#define mchk_c_os_bugcheck (72<<1) +#define mchk_c_dcperr (73<<1) +#define mchk_c_icperr (74<<1) +#define mchk_c_retryable_ird (75<<1) +#define mchk_c_proc_hrd_error (76<<1) +#define mchk_c_scperr (77<<1) +#define mchk_c_bcperr (78<<1) +//; mchk codes above 255 reserved for platform specific errors + + +#define mchk_c_read_nxm (256<<1) +#define mchk_c_sys_hrd_error (257<<1) +#define mchk_c_sys_ecc (258<<1) + +// _DEFEND MCHK_CODES,_GBL,DEF +// .ENDM + +// .MACRO _EV5_MM,_GBL +// _DEFINI _EV5_MM,_GBL + +#define page_seg_size_bits 10 +#define page_offset_size_bits 13 +#define page_size_bytes 8192 +#define va_size_bits 43 +#define pa_size_bits 45 + +// _DEFEND _EV5_MM,_GBL,DEF +// .ENDM + +// .MACRO _PALTEMP,_GBL +// _DEFINI _PALTEMP,_GBL + +// replaced by ev5_defs.h #define pt0 (0x140) +// replaced by ev5_defs.h #define pt1 (0x141) +// replaced by ev5_defs.h #define pt2 (0x142) +#define pt_entuna (0x142) +// replaced by ev5_defs.h #define pt3 (0x143) +#define pt_impure (0x143) +// replaced by ev5_defs.h #define pt4 (0x144) +// replaced by ev5_defs.h #define pt5 (0x145) +// replaced by ev5_defs.h #define pt6 (0x146) +// replaced by ev5_defs.h #define pt7 (0x147) +#define pt_entif (0x147) +// replaced by ev5_defs.h #define pt8 (0x148) +#define pt_intmask (0x148) +// replaced by ev5_defs.h #define pt9 (0x149) +#define pt_entsys (0x149) +#define pt_ps (0x149) +// replaced by ev5_defs.h #define pt10 (0x14a) +// replaced by ev5_defs.h #define pt11 (0x14b) +#define pt_trap (0x14b) +#define pt_entint (0x14b) +// replaced by ev5_defs.h #define pt12 (0x14c) +#define pt_entarith (0x14c) +// replaced by ev5_defs.h #define pt13 (0x14d) +#define pt_sys0 (0x14d) +// replaced by ev5_defs.h #define pt14 (0x14e) +#define pt_sys1 (0x14e) +// replaced by ev5_defs.h #define pt15 (0x14f) +#define pt_sys2 (0x14f) +// replaced by ev5_defs.h #define pt16 (0x150) +#define pt_whami (0x150) +#define pt_mces (0x150) +#define pt_misc (0x150) +// replaced by ev5_defs.h #define pt17 (0x151) +#define pt_scc (0x151) +#define pt_sysval (0x151) +// replaced by ev5_defs.h #define pt18 (0x152) +#define pt_prbr (0x152) +#define pt_usp (0x152) +// replaced by ev5_defs.h #define pt19 (0x153) +#define pt_ksp (0x153) +// replaced by ev5_defs.h #define pt20 (0x154) +#define pt_ptbr (0x154) +// replaced by ev5_defs.h #define pt21 (0x155) +#define pt_vptbr (0x155) +#define pt_entmm (0x155) +// replaced by ev5_defs.h #define pt22 (0x156) +#define pt_scbb (0x156) +#define pt_kgp (0x156) +// replaced by ev5_defs.h #define pt23 (0x157) +#define pt_pcbb (0x157) + + +#define pt_misc_v_switch 48 +#define pt_misc_v_cm 56 + +// _DEFEND _PALTEMP,_GBL,DEF +// .ENDM + +// .MACRO _OSF_MMCSR_DEF,_GBL +// _DEFINI OSFMMCSR,_GBL + +#define mmcsr_c_tnv 0 +#define mmcsr_c_acv 1 +#define mmcsr_c_for 2 +#define mmcsr_c_foe 3 +#define mmcsr_c_fow 4 + +// _DEFEND OSFMMCSR,_GBL,DEF +// .ENDM + +// .MACRO _MM_STAT_DEF,_GBL +// _DEFINI MMSTATDEF,_GBL + +#define mm_stat_m_opcode (0x3F) +#define mm_stat_m_ra (0x1F) +#define evx_opc_sync (0x18) +#define EVX_OPC_SYNC (0x18) +#define evx_opc_hw_ld (0x1B) + +// _DEFEND MMSTATDEF,_GBL,DEF +// .ENDM + +// .MACRO _OSF_A0_DEF,_GBL +// _DEFINI OSFA0DEF,_GBL + +#define osf_a0_bpt (0x0) +#define osf_a0_bugchk (0x1) +#define osf_a0_gentrap (0x2) +#define osf_a0_fen (0x3) +#define osf_a0_opdec (0x4) + +// _DEFEND OSFA0DEF,_GBL,DEF +// .ENDM + +// .MACRO _EV5_IPLDEF,_GBL +// _DEFINI EV5_IPLDEF,_GBL + +#define ipl_machine_check 31 +#define ipl_powerfail 30 +#define ipl_perf_count 29 +#define ipl_clock 22 +#define ipl_interprocessor 22 + +// _DEFEND EV5_IPLDEF,_GBL,DEF +// .ENDM + +#endif diff --git a/system/alpha/palcode/fromHudsonMacros.h b/system/alpha/palcode/fromHudsonMacros.h new file mode 100644 index 000000000..4b22d87ac --- /dev/null +++ b/system/alpha/palcode/fromHudsonMacros.h @@ -0,0 +1,145 @@ +#ifndef HUDSON_MACROS_LOADED +#define HUDSON_MACROS_LOADED 1 + +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:16 1995] SF: [macros.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** macros.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 PALcode macro definitions +** +** AUTHOR: ER +** +** CREATION DATE: 29-Nov-1993 +** +** $Id: fromHudsonMacros.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: fromHudsonMacros.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:46:23 boyle +** Initial revision +** +** Revision 1.5 1994/07/08 17:03:12 samberg +** Changes to support platform specific additions +** +** Revision 1.4 1994/05/20 19:24:19 ericr +** Moved STALL macro from osfpal.s to here +** Added LDLI macro +** +** Revision 1.3 1994/05/20 18:08:14 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.2 1994/02/28 18:45:51 ericr +** Fixed EGORE related bugs +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + +#define STALL \ + mfpr r31, pt0 + +#define NOP \ + bis $31, $31, $31 + +/* +** Align code on an 8K byte page boundary. +*/ + +#define ALIGN_PAGE \ + .align 13 + +/* +** Align code on a 32 byte block boundary. +*/ + +#define ALIGN_BLOCK \ + .align 5 + +/* +** Align code on a quadword boundary. +*/ + +#define ALIGN_BRANCH \ + .align 3 + +/* +** Hardware vectors go in .text 0 sub-segment. +*/ + +#define HDW_VECTOR(offset) \ + . = offset + +/* +** Privileged CALL_PAL functions are in .text 1 sub-segment. +*/ + +#define CALL_PAL_PRIV(vector) \ + . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6)) + +/* +** Unprivileged CALL_PAL functions are in .text 1 sub-segment, +** the privileged bit is removed from these vectors. +*/ + +#define CALL_PAL_UNPRIV(vector) \ + . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6)) + +/* +** Implements a load "immediate" longword function +*/ +#define LDLI(reg,val) \ + ldah reg, ((val+0x8000) >> 16)(zero); \ + lda reg, (val&0xffff)(reg) + + + +#endif diff --git a/system/alpha/palcode/fromHudsonOsf.h b/system/alpha/palcode/fromHudsonOsf.h new file mode 100644 index 000000000..f9cb2f747 --- /dev/null +++ b/system/alpha/palcode/fromHudsonOsf.h @@ -0,0 +1,554 @@ +#ifndef FROMHUDSONOSF_INCLUDED +#define FROMHUDSONOSF_INCLUDED 1 +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __OSF_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** osf.h +** +** MODULE DESCRIPTION: +** +** OSF/1 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: fromHudsonOsf.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.1 1995/11/18 01:46:31 boyle +** Initial revision +** +** Revision 1.11 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.10 1994/09/26 14:17:47 samberg +** Complete VICE work and EB164/SD164 breakout. +** +** Revision 1.9 1994/07/26 17:39:10 samberg +** Changes for SD164. +** +** Revision 1.8 1994/07/08 17:03:48 samberg +** Changes to support platform specific additions +** +** Revision 1.7 1994/05/20 19:23:51 ericr +** Moved STACK_FRAME macro from osfpal.s to here +** +** Revision 1.6 1994/05/20 18:08:19 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.5 1994/01/11 18:43:33 ericr +** Removed PAL version/revision and size constants +** +** Revision 1.4 1994/01/05 16:22:32 ericr +** Added more SCB vector offsets and MCHK error code +** +** Revision 1.3 1994/01/03 19:35:40 ericr +** Derive mask definitions from field constants +** +** Revision 1.2 1993/12/22 20:43:01 eric +** Added mask definitions for MCES bits +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + +/* +** Seg0 and Seg1 Virtual Address (VA) Format +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <42:33> 10 SEG1 First level page table offset +** <32:23> 10 SEG2 Second level page table offset +** <22:13> 10 SEG3 Third level page table offset +** <12:00> 13 OFFSET Byte within page offset +*/ + +#define VA_V_SEG1 33 +#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number +** <31:16> 16 SW Reserved for software +** <15:14> 2 RSV0 Reserved for hardware SBZ +** <13> 1 UWE User Write Enable +** <12> 1 KWE Kernel Write Enable +** <11:10> 2 RSV1 Reserved for hardware SBZ +** <9> 1 URE User Read Enable +** <8> 1 KRE Kernel Read Enable +** <7> 1 RSV2 Reserved for hardware SBZ +** <6:5> 2 GH Granularity Hint +** <4> 1 ASM Address Space Match +** <3> 1 FOE Fault On Execute +** <2> 1 FOW Fault On Write +** <1> 1 FOR Fault On Read +** <0> 1 V Valid +*/ + +#define PTE_V_PFN 32 +#define PTE_M_PFN 0xFFFFFFFF00000000 +#define PTE_V_SW 16 +#define PTE_M_SW 0x00000000FFFF0000 +#define PTE_V_UWE 13 +#define PTE_M_UWE (1< 1 CM Current Mode +** <2:0> 3 IPL Interrupt Priority Level +**/ + +#define PS_V_CM 3 +#define PS_M_CM (1< 1 MIP Machine check in progress +** <1> 1 SCE System correctable error in progress +** <2> 1 PCE Processor correctable error in progress +** <3> 1 DPC Disable PCE error reporting +** <4> 1 DSC Disable SCE error reporting +*/ + +#define MCES_V_MIP 0 +#define MCES_M_MIP (1< 8 ID Who-Am-I identifier +** <15:8> 1 SWAP Swap PALcode flag - character 'S' +*/ + +#define WHAMI_V_SWAP 8 +#define WHAMI_M_SWAP (1<> 16)(zero); \ + lda reg, (val&0xffff)(reg) + diff --git a/system/alpha/palcode/osf.h b/system/alpha/palcode/osf.h new file mode 100644 index 000000000..316d83cf1 --- /dev/null +++ b/system/alpha/palcode/osf.h @@ -0,0 +1,545 @@ +/* + * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h] + * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ] + */ +#define __OSF_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** osf.h +** +** MODULE DESCRIPTION: +** +** OSF/1 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id: osf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ +** +** MODIFICATION HISTORY: +** +** $Log: osf.h,v $ +** Revision 1.1.1.1 1997/10/30 23:27:19 verghese +** current 10/29/97 +** +** Revision 1.11 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.10 1994/09/26 14:17:47 samberg +** Complete VICE work and EB164/SD164 breakout. +** +** Revision 1.9 1994/07/26 17:39:10 samberg +** Changes for SD164. +** +** Revision 1.8 1994/07/08 17:03:48 samberg +** Changes to support platform specific additions +** +** Revision 1.7 1994/05/20 19:23:51 ericr +** Moved STACK_FRAME macro from osfpal.s to here +** +** Revision 1.6 1994/05/20 18:08:19 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.5 1994/01/11 18:43:33 ericr +** Removed PAL version/revision and size constants +** +** Revision 1.4 1994/01/05 16:22:32 ericr +** Added more SCB vector offsets and MCHK error code +** +** Revision 1.3 1994/01/03 19:35:40 ericr +** Derive mask definitions from field constants +** +** Revision 1.2 1993/12/22 20:43:01 eric +** Added mask definitions for MCES bits +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + +/* +** Seg0 and Seg1 Virtual Address (VA) Format +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <42:33> 10 SEG1 First level page table offset +** <32:23> 10 SEG2 Second level page table offset +** <22:13> 10 SEG3 Third level page table offset +** <12:00> 13 OFFSET Byte within page offset +*/ + +#define VA_V_SEG1 33 +#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number +** <31:16> 16 SW Reserved for software +** <15:14> 2 RSV0 Reserved for hardware SBZ +** <13> 1 UWE User Write Enable +** <12> 1 KWE Kernel Write Enable +** <11:10> 2 RSV1 Reserved for hardware SBZ +** <9> 1 URE User Read Enable +** <8> 1 KRE Kernel Read Enable +** <7> 1 RSV2 Reserved for hardware SBZ +** <6:5> 2 GH Granularity Hint +** <4> 1 ASM Address Space Match +** <3> 1 FOE Fault On Execute +** <2> 1 FOW Fault On Write +** <1> 1 FOR Fault On Read +** <0> 1 V Valid +*/ + +#define PTE_V_PFN 32 +#define PTE_M_PFN 0xFFFFFFFF00000000 +#define PTE_V_SW 16 +#define PTE_M_SW 0x00000000FFFF0000 +#define PTE_V_UWE 13 +#define PTE_M_UWE (1< 1 CM Current Mode +** <2:0> 3 IPL Interrupt Priority Level +**/ + +#define PS_V_CM 3 +#define PS_M_CM (1< 1 MIP Machine check in progress +** <1> 1 SCE System correctable error in progress +** <2> 1 PCE Processor correctable error in progress +** <3> 1 DPC Disable PCE error reporting +** <4> 1 DSC Disable SCE error reporting +*/ + +#define MCES_V_MIP 0 +#define MCES_M_MIP (1< 8 ID Who-Am-I identifier +** <15:8> 1 SWAP Swap PALcode flag - character 'S' +*/ + +#define WHAMI_V_SWAP 8 +#define WHAMI_M_SWAP (1< virt ref bug +// DB 0.3 11-Jan-1993 rearrange trap entry points +// DB 0.4 01-Feb-1993 add tbi +// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal +// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14) +// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC +// Bug: typo on register number for store in wrunique +// Bug: rti to kern uses r16 as scratch +// Bug: callsys saving wrong value in pt_usp +// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp +// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice +// Bug: rti stl_c could corrupt the stack +// Bug: unaligned returning wrong value in r17 (or should be and) +// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt +// DB 0.11 23-Feb-1993 Turn caches on in reset flow +// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow +// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses +// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS +// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES +// DB 0.16 12-May-1993 Update reset +// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows +// Bug: in wrmces, not clearing DPC, DSC +// Update swppal +// Add pal bugchecks, pal_save_state, pal_restore_state +// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps. +// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn +// DB 0.18 26-May-1993 PVC fixes +// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores +// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl +// Bug: exc_addr was being loaded before stores that could dtb_miss in the following +// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN +// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines: +// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN:: +// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler: +// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN:: +// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles +// JM 0.22 28-jul-1993 Add WRIPIR instruction +// JM 0.23 05-aug-1993 Bump version number for release +// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation +// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals; +// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode), +// and SWPCTX +// JM 0.26 07-oct-1993 Re-implement pal_version +// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM +// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush +// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead +// of mm_stat. mm_stat contains original opcode, not hw_ld. +// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys +// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0 +// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0 +// JM 0.33 24-nov-1993 save/restore_state - +// BUG: use ivptbr to restore mvptbr +// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit +// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors +// JM 0.34 20-dec-1993 BUG: set r11 to kernel for ksnv halt case +// BUG: generate ksnv halt when tb miss on kernel stack accesses +// save exc_addr in r14 for invalid_dpte stack builder +// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in +// the same shadow +// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS +// New palcode restiction: mt icsr --> 3 bubbles to hw_rei --affects wrfen +// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions +// Hide impure area manipulations in macros +// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st +// Add some pvc_violate statements +// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality; +// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments +// Add code to ensure fen bit set in icsr before ldt +// conditionally compile rax_more_reset out. +// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here +// move rax reset stuff to ev5_osf_system_pal.m64 +// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow +// and performance monitoring bits +// Change to save_state routine to save more iprs. +// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in +// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems) +// remove_save_state,remove_restore_state;fix new pvc violation in save_state +// JM 0.42 22-feb-1994 BUG: save_state overwriting r3 +// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr +// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions +// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem) +// New pal restriction in pal_restore_state: icsr->floating instr = 3 bubbles +// Add exc_sum and exc_mask to pal_save_state (not restore) +// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure +// area. +// Add performance counter support to swpctx and wrperfmon +// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix) +// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts +// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is +// taken in the interrupt flow, stack is pushed twice. +// SWPPAL - update to support ECO 59 to allow 0 as a valid address +// Add itb flush to save/restore state routines +// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but +// conforms to itbia restriction. +// Added enable_physical_console flag (for enter/exit console routines only) +// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a +// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and +// nmiss_fetch_err to nmiss_fetch_ldr31_err. +// JM 1.00 1-aug-1994 Add pass2 support (swpctx) +// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2 +// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2) +// Moved perfmon code here from system file. +// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1) +// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit. +// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change +// after ISR read, but we won't catch the ISR update. reverse order +// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31 +// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code) +// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to +// DTBMISS_SINGLE if not in palmode. +// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame +// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox +// superpage mode in User mode and re-enable in kernel mode. +// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this. +// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2 +// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid +// cpu bug. +// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state +// ES 1.13 17-mar-1995 Refine osf_chm_fix +// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix +// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state +// Force pvc checking of exit_console +// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0 +// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting) +// instead of xor to maintain previous mode in pt_misc +// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does +// not have pme set. The bits in icsr maintain the master enable state. +// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable +// +#define vmaj 1 +#define vmin 18 +#define vms_pal 1 +#define osf_pal 2 +#define pal_type osf_pal +#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) +//- + +// .sbttl "PALtemp register usage" + +//+ +// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage +// for these PALtemps: +// +// pt0 local scratch +// pt1 local scratch +// pt2 entUna pt_entUna +// pt3 CPU specific impure area pointer pt_impure +// pt4 memory management temp +// pt5 memory management temp +// pt6 memory management temp +// pt7 entIF pt_entIF +// pt8 intmask pt_intmask +// pt9 entSys pt_entSys +// pt10 +// pt11 entInt pt_entInt +// pt12 entArith pt_entArith +// pt13 reserved for system specific PAL +// pt14 reserved for system specific PAL +// pt15 reserved for system specific PAL +// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces +// pt17 sysval pt_sysval +// pt18 usp pt_usp +// pt19 ksp pt_ksp +// pt20 PTBR pt_ptbr +// pt21 entMM pt_entMM +// pt22 kgp pt_kgp +// pt23 PCBB pt_pcbb +// +//- + +// .sbttl "PALshadow register usage" +// +//+ +// +// EV5 shadows R8-R14 and R25 when in PALmode and ICSR = 1. +// This maps the OSF PAL usage of R8 - R14 and R25: +// +// r8 ITBmiss/DTBmiss scratch +// r9 ITBmiss/DTBmiss scratch +// r10 ITBmiss/DTBmiss scratch +// r11 PS +// r12 local scratch +// r13 local scratch +// r14 local scratch +// r25 local scratch +// +// +//- + +// .sbttl "ALPHA symbol definitions" +// _OSF_PSDEF GLOBAL +// _OSF_PTEDEF GLOBAL +// _OSF_VADEF GLOBAL +// _OSF_PCBDEF GLOBAL +// _OSF_SFDEF GLOBAL +// _OSF_MMCSR_DEF GLOBAL +// _SCBDEF GLOBAL +// _FRMDEF GLOBAL +// _EXSDEF GLOBAL +// _OSF_A0_DEF GLOBAL +// _MCESDEF GLOBAL + +// .sbttl "EV5 symbol definitions" + +// _EV5DEF +// _PALTEMP +// _MM_STAT_DEF +// _EV5_MM +// _EV5_IPLDEF + +// _HALT_CODES GLOBAL +// _MCHK_CODES GLOBAL + +// _PAL_IMPURE +// _PAL_LOGOUT + + + + +// .sbttl "PALcode configuration options" + +// There are a number of options that may be assembled into this version of +// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit +// the following). The options that can be adjusted cause the resultant PALcode +// to reflect the desired target system. + + +#define osfpal 1 // This is the PALcode for OSF. + +#ifndef rawhide_system + +#define rawhide_system 0 +#endif + + +#ifndef real_mm +// Page table translation vs 1-1 mapping +#define real_mm 1 +#endif + + +#ifndef rax_mode + +#define rax_mode 0 +#endif + +#ifndef egore +// End of reset flow starts a program at 200000(hex). +#define egore 1 +#endif + +#ifndef acore +// End of reset flow starts a program at 40000(hex). +#define acore 0 +#endif + + +// assume acore+egore+rax_mode lt 2 // Assertion checker + +#ifndef beh_model +// EV5 behavioral model specific code +#define beh_model 1 +#endif + +#ifndef init_cbox +// Reset flow init of Bcache and Scache +#define init_cbox 1 +#endif + +#ifndef disable_crd +// Decides whether the reset flow will disable +#define disable_crd 0 +#endif + + // correctable read interrupts via ICSR +#ifndef perfmon_debug +#define perfmon_debug 0 +#endif + +#ifndef icflush_on_tbix +#define icflush_on_tbix 0 +#endif + +#ifndef remove_restore_state +#define remove_restore_state 0 +#endif + +#ifndef remove_save_state +#define remove_save_state 0 +#endif + +#ifndef enable_physical_console +#define enable_physical_console 0 +#endif + +#ifndef ev5_p1 +#define ev5_p1 0 +#endif + +#ifndef ev5_p2 +#define ev5_p2 1 +#endif + +// assume ev5_p1+ev5_p2 eq 1 + +#ifndef ldvpte_bug_fix +#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow. +#endif + +#ifndef spe_fix +// If set, disable super-page mode in user mode and re-enable +#define spe_fix 0 +#endif + // in kernel. Workaround for cpu bug. +#ifndef build_fixed_image +#define build_fixed_image 0 +#endif + + +#ifndef fill_err_hack +// If set, disable fill_error mode in user mode and re-enable +#define fill_err_hack 0 +#endif + + // in kernel. Workaround for cpu bug. + +// .macro hw_rei_spe +// .iif eq spe_fix, hw_rei +//#if spe_fix != 0 +// +// +//#define hw_rei_chm_count hw_rei_chm_count + 1 +// p4_fixup_label \hw_rei_chm_count +// .iif eq build_fixed_image, br r31, hw_rei_update_spe +// .iif ne build_fixed_image, hw_rei +//#endif +// +// .endm + +// Add flag "osf_chm_fix" to enable dcache in user mode only +// to avoid cpu bug. + +#ifndef osf_chm_fix +// If set, enable D-Cache in +#define osf_chm_fix 0 +#endif + +#if osf_chm_fix != 0 +// user mode only. +#define hw_rei_chm_count 0 +#endif + +#if osf_chm_fix != 0 + +#define hw_rei_stall_chm_count 0 +#endif + +#ifndef enable_p4_fixups + +#define enable_p4_fixups 0 +#endif + + // If set, do EV5 Pass 4 fixups +#if spe_fix == 0 + +#define osf_chm_fix 0 +#endif + +#if spe_fix == 0 + +#define enable_p4_fixups 0 +#endif + + // Only allow fixups if fix enabled + + //Turn off fill_errors and MEM_NEM in user mode +// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_ +// //save r22,r23,r24 +// stqp r22, 0x150(r31) //add +// stqp r23, 0x158(r31) //contents +// stqp r24, 0x160(r31) //bit mask +// +// lda r22, 0x82(r31) +// ldah r22, 0x8740(r22) +// sll r22, 8, r22 +// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK +// bis r23,r31,r23 +// +// lda r24, 0x8(r31) // r24 <- MEM_NEM bit +// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode +// bic r23, r24, r23 // set fillerr_en bit +// br r31, L20_ // ELSE +//L10_: bis r23, r24, r23 // clear fillerr_en bit +//L20_: // ENDIF +// +// stlp r23, 0x80(r22) // write back the CIA_MASK register +// mb +// ldlp r23, 0x80(r22) +// bis r23,r31,r23 +// mb +// +// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL +// ldah r22, 0x8740(r22) +// sll r22, 8, r22 +// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL +// bis r23,r31,r23 +// +// +// lda r24, 0x400(r31) // r9 <- fillerr_en bit +// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode +// bic r23, r24, r23 // set fillerr_en bit +// br r31, L40_ // ELSE +//L30_: bis r23, r24, r23 // clear fillerr_en bit +//L40_: // ENDIF +// +// stlp r23, 0(r22) // write back the CIA_CTRL register +// mb +// ldlp r23, 0(r22) +// bis r23,r31,r23 +// mb +// +// //restore r22,r23,r24 +// ldqp r22, 0x150(r31) +// ldqp r23, 0x158(r31) +// ldqp r24, 0x160(r31) +// +// .endm + +// multiprocessor support can be enabled for a max of n processors by +// setting the following to the number of processors on the system. +// Note that this is really the max cpuid. + +#ifndef max_cpuid +#define max_cpuid 8 +#endif + +#ifndef osf_svmin // platform specific palcode version number +#define osf_svmin 0 +#endif + + +#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) + +// .mcall ldqp // override macro64 definition with macro from library +// .mcall stqp // override macro64 definition with macro from library + + +// .psect _pal,mix +// huh pb pal_base: +// huh pb #define current_block_base . - pal_base + +// .sbttl "RESET - Reset Trap Entry Point" +//+ +// RESET - offset 0000 +// Entry: +// Vectored into via hardware trap on reset, or branched to +// on swppal. +// +// r0 = whami +// r1 = pal_base +// r2 = base of scratch area +// r3 = halt code +// +// +// Function: +// +//- + + .text 0 + . = 0x0000 + .globl Pal_Base +Pal_Base: + HDW_VECTOR(PAL_RESET_ENTRY) +Trap_Reset: + nop +#ifdef SIMOS + /* + * store into r1 + */ + br r1,sys_reset +#else + /* following is a srcmax change */ + + DEBUGSTORE(0x41) + /* The original code jumped using r1 as a linkage register to pass the base + of PALcode to the platform specific code. We use r1 to pass a parameter + from the SROM, so we hardcode the address of Pal_Base in platform.s + */ + br r31, sys_reset +#endif + + // Specify PAL version info as a constant + // at a known location (reset + 8). + + .long osfpal_version_l // ! ! + .long osfpal_version_h // ! + .long 0 + .long 0 +pal_impure_start: + .quad 0 +pal_debug_ptr: + .quad 0 // reserved for debug pointer ; 20 +#if beh_model == 0 + + +#if enable_p4_fixups != 0 + + + .quad 0 + .long p4_fixup_hw_rei_fixup_table +#endif + +#else + + .quad 0 // + .quad 0 //0x0030 + .quad 0 + .quad 0 //0x0040 + .quad 0 + .quad 0 //0x0050 + .quad 0 + .quad 0 //0x0060 + .quad 0 +pal_enter_cns_address: + .quad 0 //0x0070 -- address to jump to from enter_console + .long <+1> //0x0078 -- offset to sys_exit_console (set palmode bit) +#endif + + + + +// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point" + +//+ +// IACCVIO - offset 0080 +// Entry: +// Vectored into via hardware trap on Istream access violation or sign check error on PC. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV) +// a2 <- -1 (for ifetch fault) +// vector via entMM +//- + + HDW_VECTOR(PAL_IACCVIO_ENTRY) +Trap_Iaccvio: + DEBUGSTORE(0x42) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS + bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_IACCVIO_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bic r14, 3, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // pass mm_csr as a1 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entmm // get entry point + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r16, osfsf_pc(sp) // save pc + stq r29, osfsf_gp(sp) // save gp + + mtpr r13, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + subq r31, 1, r18 // pass flag of istream, as a2 + hw_rei_spe + + +// .sbttl "INTERRUPT- Interrupt Trap Entry Point" + +//+ +// INTERRUPT - offset 0100 +// Entry: +// Vectored into via trap on hardware interrupt +// +// Function: +// check for halt interrupt +// check for passive release (current ipl geq requestor) +// if necessary, switch to kernel mode +// push stack frame, update ps (including current mode and ipl copies), sp, and gp +// pass the interrupt info to the system module +// +//- + + + HDW_VECTOR(PAL_INTERRUPT_ENTRY) +Trap_Interrupt: + mfpr r13, ev5__intid // Fetch level of interruptor + mfpr r25, ev5__isr // Fetch interrupt summary register + + srl r25, isr_v_hlt, r9 // Get HLT bit + mfpr r14, ev5__ipl + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern + blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set + + cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl + bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl + + and r11, osfps_m_mode, r10 // get mode bit + beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel + + mtpr r30, pt_usp // save user stack + mfpr r30, pt_ksp // get kern stack + +TRAP_INTERRUPT_10_: + lda sp, (0-osfsf_c_size)(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r11, osfsf_ps(sp) // save ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // push gp + stq r16, osfsf_a0(sp) // a0 + +// pvc_violate 354 // ps is cleared anyway, if store to stack faults. + mtpr r31, ev5__ps // Set Ibox current mode to kernel + stq r17, osfsf_a1(sp) // a1 + + stq r18, osfsf_a2(sp) // a2 + subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL + + srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7. + subq r13, 0x1d, r9 // Check for 1d, 1e, 1f + + cmovge r9, r8, r12 // if .ge. 1d, then take shifted value + bis r12, r31, r11 // set new ps + + mfpr r12, pt_intmask + and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) + +#ifdef SIMOS + /* + * Lance had space problems. We don't. + */ + extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL + mfpr r29, pt_kgp // update gp + mtpr r14, ev5__ipl // load the new IPL into Ibox +#else +// Moved the following three lines to sys_interrupt to make room for debug +// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL +// mfpr r29, pt_kgp // update gp + +// mtpr r14, ev5__ipl // load the new IPL into Ibox +#endif + br r31, sys_interrupt // Go handle interrupt + + + +// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point" + +//+ +// ITBMISS - offset 0180 +// Entry: +// Vectored into via hardware trap on Istream translation buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +// +//- + + HDW_VECTOR(PAL_ITB_MISS_ENTRY) +Trap_Itbmiss: +#if real_mm == 0 + + + // Simple 1-1 va->pa mapping + + nop // Pad to align to E1 + mfpr r8, exc_addr + + srl r8, page_offset_size_bits, r9 + sll r9, 32, r9 + + lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE + mtpr r9, itb_pte // E1 + + hw_rei_stall // Nital says I don't have to obey shadow wait rule here. +#else + + // Real MM mapping + nop + mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. + + nop + mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. + +pal_itb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + mtpr r10, exc_addr // Restore exc_address if there was a trap. + + mfpr r31, ev5__va // Unlock VA in case there was a double miss + nop + + and r8, osfpte_m_foe, r25 // Look for FOE set. + blbc r8, invalid_ipte_handler // PTE not valid. + + nop + bne r25, foe_ipte_handler // FOE is set + + nop + mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. + + hw_rei_stall // + +#endif + + + + +// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point" + +//+ +// DTBMISS_SINGLE - offset 0200 +// Entry: +// Vectored into via hardware trap on Dstream single translation buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +//- + + HDW_VECTOR(PAL_DTB_MISS_ENTRY) +Trap_Dtbmiss_Single: +#if real_mm == 0 + // Simple 1-1 va->pa mapping + mfpr r8, va // E0 + srl r8, page_offset_size_bits, r9 + + sll r9, 32, r9 + lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE + + mtpr r9, dtb_pte // E0 + nop // Pad to align to E0 + + + + mtpr r8, dtb_tag // E0 + nop + + nop // Pad tag write + nop + + nop // Pad tag write + nop + + hw_rei +#else + mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. + mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. + +// DEBUGSTORE(0x45) +// DEBUG_EXC_ADDR() + // Real MM mapping + mfpr r9, ev5__mm_stat // Get read/write bit. E0. + mtpr r10, pt6 // Stash exc_addr away + +pal_dtb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + nop // Pad MF VA + + mfpr r10, ev5__va // Get original faulting VA for TB load. E0. + nop + + mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0. + blbc r8, invalid_dpte_handler // Handle invalid PTE + + mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. + mfpr r10, pt6 + + // Following 2 instructions take 2 cycles + mtpr r10, exc_addr // Return linkage in case we trapped. E1. + mfpr r31, pt0 // Pad the write to dtb_tag + + hw_rei // Done, return +#endif + + + + +// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point" + +//+ +// DTBMISS_DOUBLE - offset 0280 +// Entry: +// Vectored into via hardware trap on Double TBmiss from single miss flows. +// +// r8 - faulting VA +// r9 - original MMstat +// r10 - original exc_addr (both itb,dtb miss) +// pt6 - original exc_addr (dtb miss flow only) +// VA IPR - locked with original faulting VA +// +// Function: +// Get PTE, if valid load TB and return. +// If not valid then take TNV/ACV exception. +// +// pt4 and pt5 are reserved for this flow. +// +// +//- + + HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) +Trap_Dtbmiss_double: +#if ldvpte_bug_fix != 0 + mtpr r8, pt4 // save r8 to do exc_addr check + mfpr r8, exc_addr + blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! + mfpr r8, pt4 // restore r8 +#endif + nop + mtpr r22, pt5 // Get some scratch space. E1. + // Due to virtual scheme, we can skip the first lookup and go + // right to fetch of level 2 PTE + sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + mtpr r21, pt4 // Get some scratch space. E1. + + srl r22, 61-page_seg_size_bits, r22 // Get Va*8 + mfpr r21, pt_ptbr // Get physical address of the page table. + + nop + addq r21, r22, r21 // Index into page table for level 2 PTE. + + sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) + + srl r22, 61-page_seg_size_bits, r22 // Get Va*8 + blbc r21, double_pte_inv // Check for Invalid PTE. + + srl r21, 32, r21 // extract PFN from PTE + sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to *8 + + addq r21, r22, r21 // Index into page table for level 3 PTE. + nop + + ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) + blbc r21, double_pte_inv // Check for invalid PTE. + + mtpr r21, ev5__dtb_pte // Write the PTE. E0. + mfpr r22, pt5 // Restore scratch register + + mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. + mfpr r21, pt4 // Restore scratch register + + nop // Pad write to tag. + nop + + nop // Pad write to tag. + nop + + hw_rei + + + +// .sbttl "UNALIGN -- Dstream unalign trap" +//+ +// UNALIGN - offset 0300 +// Entry: +// Vectored into via hardware trap on unaligned Dstream reference. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- Opcode +// a2 <- src/dst register number +// vector via entUna +//- + + HDW_VECTOR(PAL_UNALIGN_ENTRY) +Trap_Unalign: +/* DEBUGSTORE(0x47)*/ + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss + mfpr r14, exc_addr // get pc + + srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits + blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL + + blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m + // not set, must be a load + and r13, 0x1F, r8 // isolate ra + + cmpeq r8, 0x1F, r8 // check for r31/F31 + bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault + +UNALIGN_NO_DISMISS: + bis r11, r31, r12 // Save PS + bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +UNALIGN_NO_DISMISS_10_: + mfpr r25, ev5__va // Unlock VA + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + mtpr r25, pt0 // Stash VA + stq r18, osfsf_a2(sp) // a2 + + stq r11, osfsf_ps(sp) // save old ps + srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode + + stq r29, osfsf_gp(sp) // save gp + addq r14, 4, r14 // inc PC past the ld/st + + stq r17, osfsf_a1(sp) // a1 + and r25, mm_stat_m_opcode, r17// Clean opocde for a1 + + stq r16, osfsf_a0(sp) // save regs + mfpr r16, pt0 // a0 <- va/unlock + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entuna // get entry point + + + bis r12, r31, r11 // update ps + br r31, unalign_trap_cont + + + + +// .sbttl "DFAULT - Dstream Fault Trap Entry Point" + +//+ +// DFAULT - offset 0380 +// Entry: +// Vectored into via hardware trap on dstream fault or sign check error on DVA. +// +// Function: +// Ignore faults on FETCH/FETCH_M +// Check for DFAULT in PAL +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) +// a2 <- R/W +// vector via entMM +// +//- + HDW_VECTOR(PAL_D_FAULT_ENTRY) +Trap_Dfault: +// DEBUGSTORE(0x48) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r13, ev5__mm_stat // Get mmstat + mfpr r8, exc_addr // get pc, preserve r14 + + srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits + blbs r8, dfault_in_pal + + bis r8, r31, r14 // move exc_addr to correct place + bis r11, r31, r12 // Save PS + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + and r9, mm_stat_m_opcode, r9 // Clean all but opcode + + cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + + //dismiss exception if load to r31/f31 + blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits + + and r9, 0x1F, r9 // isolate rnum + nop + + cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + +dfault_no_dismiss: + and r13, 0xf, r13 // Clean extra bits in mm_stat + bge r25, dfault_trap_cont // no stack swap needed if cm=kern + + + mtpr r30, pt_usp // save user stack + bis r31, r31, r12 // Set new PS + + mfpr r30, pt_ksp + br r31, dfault_trap_cont + + + + + +// .sbttl "MCHK - Machine Check Trap Entry Point" + +//+ +// MCHK - offset 0400 +// Entry: +// Vectored into via hardware trap on machine check. +// +// Function: +// +//- + + HDW_VECTOR(PAL_MCHK_ENTRY) +Trap_Mchk: + DEBUGSTORE(0x49) + mtpr r31, ic_flush_ctl // Flush the Icache + br r31, sys_machine_check + + + + +// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point" + +//+ +// OPCDEC - offset 0480 +// Entry: +// Vectored into via hardware trap on illegal opcode. +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +//- + + HDW_VECTOR(PAL_OPCDEC_ENTRY) +Trap_Opcdec: + DEBUGSTORE(0x4a) +//simos DEBUG_EXC_ADDR() + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + bis r11, r31, r12 // Save PS + bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_OPCDEC_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + addq r14, 4, r14 // inc pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r11, osfsf_ps(sp) // save old ps + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r17, osfsf_a1(sp) // a1 + + stq r29, osfsf_gp(sp) // save gp + stq r14, osfsf_pc(sp) // save pc + + bis r12, r31, r11 // update ps + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei, E1 + + mfpr r29, pt_kgp // get the kgp, E1 + + hw_rei_spe // done, E1 + + + + + + +// .sbttl "ARITH - Arithmetic Exception Trap Entry Point" + +//+ +// ARITH - offset 0500 +// Entry: +// Vectored into via hardware trap on arithmetic excpetion. +// +// Function: +// Build stack frame +// a0 <- exc_sum +// a1 <- exc_mask +// a2 <- unpred +// vector via entArith +// +//- + HDW_VECTOR(PAL_ARITH_ENTRY) +Trap_Arith: + DEBUGSTORE(0x4b) + and r11, osfps_m_mode, r12 // get mode bit + mfpr r31, ev5__va // unlock mbox + + bis r11, r31, r25 // save ps + mfpr r14, exc_addr // get pc + + nop + blbs r14, pal_pal_bug_check // arith trap from PAL + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + beq r12, TRAP_ARITH_10_ // if zero we are in kern now + + bis r31, r31, r25 // set the new ps + mtpr r30, pt_usp // save user stack + + nop + mfpr r30, pt_ksp // get kern stack + +TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + nop // Pad current mode write and stq + mfpr r13, ev5__exc_sum // get the exc_sum + + mfpr r12, pt_entarith + stq r14, osfsf_pc(sp) // save pc + + stq r17, osfsf_a1(sp) + mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle + + stq r11, osfsf_ps(sp) // save ps + bis r25, r31, r11 // set new ps + + stq r16, osfsf_a0(sp) // save regs + srl r13, exc_sum_v_swc, r16// shift data to correct position + + stq r18, osfsf_a2(sp) +// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow + mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask + + stq r29, osfsf_gp(sp) + mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 + + mfpr r29, pt_kgp // get the kern gp - E1 + hw_rei_spe // done - E1 + + + + + + +// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point" + +//+ +// FEN - offset 0580 +// Entry: +// Vectored into via hardware trap on illegal FP op. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +//- + + HDW_VECTOR(PAL_FEN_ENTRY) +Trap_Fen: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + mfpr r13, ev5__icsr + nop + + bis r11, r31, r12 // Save PS + bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_FEN_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0 + + + stq r16, osfsf_a0(sp) // save regs + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r11, osfsf_ps(sp) // save old ps + + stq r29, osfsf_gp(sp) // save gp + bis r12, r31, r11 // set new ps + + stq r17, osfsf_a1(sp) // a1 + blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC. + + bis r31, osf_a0_fen, r16 // set a0 + stq r14, osfsf_pc(sp) // save pc + + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei -E1 + + mfpr r29, pt_kgp // get the kgp -E1 + + hw_rei_spe // done -E1 + +// FEN trap was taken, but the fault is really opcdec. + ALIGN_BRANCH +fen_to_opcdec: + addq r14, 4, r14 // save PC+4 + bis r31, osf_a0_opdec, r16 // set a0 + + stq r14, osfsf_pc(sp) // save pc + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + hw_rei_spe // done + + + +// .sbttl "Misc handlers" + // Start area for misc code. +//+ +//dfault_trap_cont +// A dfault trap has been taken. The sp has been updated if necessary. +// Push a stack frame a vector via entMM. +// +// Current state: +// r12 - new PS +// r13 - MMstat +// VA - locked +// +//- + ALIGN_BLOCK +dfault_trap_cont: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r25, ev5__va // Fetch VA/unlock + + stq r18, osfsf_a2(sp) // a2 + and r13, 1, r18 // Clean r/w bit for a2 + + stq r16, osfsf_a0(sp) // save regs + bis r25, r31, r16 // a0 <- va + + stq r17, osfsf_a1(sp) // a1 + srl r13, 1, r17 // shift fault bits to right position + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entmm // get entry point + + stq r29, osfsf_gp(sp) // save gp + cmovlbs r17, 1, r17 // a2. acv overrides fox. + + mtpr r25, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + hw_rei_spe // done + +//+ +//unalign_trap_cont +// An unalign trap has been taken. Just need to finish up a few things. +// +// Current state: +// r25 - entUna +// r13 - shifted MMstat +// +//- + ALIGN_BLOCK +unalign_trap_cont: + mtpr r25, exc_addr // load exc_addr with entUna + // 1 cycle to hw_rei + + + mfpr r29, pt_kgp // get the kgp + and r13, mm_stat_m_ra, r18 // Clean Ra for a2 + + hw_rei_spe // done + + + +//+ +// dfault_in_pal +// Dfault trap was taken, exc_addr points to a PAL PC. +// r9 - mmstat right justified +// r8 - exception address +// +// These are the cases: +// opcode was STQ -- from a stack builder, KSP not valid halt +// r14 - original exc_addr +// r11 - original PS +// opcode was STL_C -- rti or retsys clear lock_flag by stack write, +// KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was LDQ -- retsys or rti stack read, KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables +// r10 - original exc_addr +// r11 - original PS +// +// +//- + ALIGN_BLOCK +dfault_in_pal: + DEBUGSTORE(0x50) + bic r8, 3, r8 // Clean PC + mfpr r9, pal_base + + mfpr r31, va // unlock VA +#if real_mm != 0 + // if not real_mm, should never get here from miss flows + + subq r9, r8, r8 // pal_base - offset + + lda r9, pal_itb_ldq-pal_base(r8) + nop + + beq r9, dfault_do_bugcheck + lda r9, pal_dtb_ldq-pal_base(r8) + + beq r9, dfault_do_bugcheck +#endif + +// +// KSP invalid halt case -- +ksp_inval_halt: + DEBUGSTORE(76) + bic r11, osfps_m_mode, r11 // set ps to kernel mode + mtpr r0, pt0 + + mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode + mtpr r31, ips + + mtpr r14, exc_addr // Set PC to instruction that caused trouble +//orig pvc_jsr updpcb, bsr=1 + bsr r0, pal_update_pcb // update the pcb + + lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt + br r31, sys_enter_console // enter the console + + ALIGN_BRANCH +dfault_do_bugcheck: + bis r10, r31, r14 // bugcheck expects exc_addr in r14 + br r31, pal_pal_bug_check + + + ALIGN_BLOCK +//+ +// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 +// On entry - +// r14 - exc_addr +// VA is locked +// +//- +dfault_fetch_ldr31_err: + mtpr r11, ev5__dtb_cm + mtpr r11, ev5__ps // Make sure ps hasn't changed + + mfpr r31, va // unlock the mbox + addq r14, 4, r14 // inc the pc to skip the fetch + + mtpr r14, exc_addr // give ibox new PC + mfpr r31, pt0 // pad exc_addr write + + hw_rei + + + + ALIGN_BLOCK +//+ +// sys_from_kern +// callsys from kernel mode - OS bugcheck machine check +// +//- +sys_from_kern: + mfpr r14, exc_addr // PC points to call_pal + subq r14, 4, r14 + + lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code + br r31, pal_pal_mchk + + +// .sbttl "Continuation of long call_pal flows" + ALIGN_BLOCK +//+ +// wrent_tbl +// Table to write *int in paltemps. +// 4 instructions/entry +// r16 has new value +// +//- +wrent_tbl: +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entint + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entarith + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entmm + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entif + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entuna + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entsys + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + ALIGN_BLOCK +//+ +// tbi_tbl +// Table to do tbi instructions +// 4 instructions per entry +//- +tbi_tbl: + // -2 tbia +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_ia // Flush DTB + mtpr r31, ev5__itb_ia // Flush ITB + +#if icflush_on_tbix != 0 + + + br r31, pal_ic_flush // Flush Icache +#else + + hw_rei_stall +#endif + + nop // Pad table + + // -1 tbiap +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_iap // Flush DTB + mtpr r31, ev5__itb_iap // Flush ITB + +#if icflush_on_tbix != 0 + + + br r31, pal_ic_flush // Flush Icache +#else + + hw_rei_stall +#endif + + nop // Pad table + + + // 0 unused +//orig pvc_jsr tbi, dest=1 + hw_rei // Pad table + nop + nop + nop + + + // 1 tbisi +//orig pvc_jsr tbi, dest=1 +#if icflush_on_tbix != 0 + + + + nop + br r31, pal_ic_flush_and_tbisi // Flush Icache + nop + nop // Pad table +#else + + nop + nop + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall +#endif + + + + // 2 tbisd +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB. + nop + + nop + hw_rei_stall + + + // 3 tbis +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB +#if icflush_on_tbix != 0 + + + br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB +#else + br r31, tbi_finish + ALIGN_BRANCH +tbi_finish: + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall +#endif + + + + ALIGN_BLOCK +//+ +// bpt_bchk_common: +// Finish up the bpt/bchk instructions +//- +bpt_bchk_common: + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + ALIGN_BLOCK +//+ +// rti_to_user +// Finish up the rti instruction +//- +rti_to_user: + mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles + mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei + + mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles + mtpr r25, pt_ksp // save off incase RTI to user + + mfpr r30, pt_usp + hw_rei_spe // and back + + + ALIGN_BLOCK +//+ +// rti_to_kern +// Finish up the rti instruction +//- +rti_to_kern: + and r12, osfps_m_ipl, r11 // clean ps + mfpr r12, pt_intmask // get int mask + + extbl r12, r11, r12 // get mask for this ipl + mtpr r25, pt_ksp // save off incase RTI to user + + mtpr r12, ev5__ipl // set the new ipl. + or r25, r31, sp // sp + +// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals + hw_rei + + ALIGN_BLOCK +//+ +// swpctx_cont +// Finish up the swpctx instruction +//- + +swpctx_cont: +#if ev5_p1 != 0 + + + bic r25, r24, r25 // clean icsr + get_impure r8 // get impure pointer + + sll r12, icsr_v_fpe, r12 // shift new fen to pos + fix_impure_ipr r8 // adjust impure pointer + + restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits + srl r23, 32, r24 // move asn to low asn pos + + ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr + srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 + + or r25, r12, r25 // icsr with new fen + sll r24, itb_asn_v_asn, r12 + +#else + + bic r25, r24, r25 // clean icsr + sll r12, icsr_v_fpe, r12 // shift new fen to pos + + ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr + srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 + + or r25, r12, r25 // icsr with new fen + srl r23, 32, r24 // move asn to low asn pos + + and r22, 1, r22 + sll r24, itb_asn_v_asn, r12 + + sll r22, icsr_v_pmp, r22 + nop + + or r25, r22, r25 // icsr with new pme +#endif + + sll r24, dtb_asn_v_asn, r24 + + subl r23, r13, r13 // gen new cc offset + mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 + + mtpr r24, dtb_asn // Load up new ASN + mtpr r25, icsr // write the icsr + + sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. + ldqp r25, osfpcb_q_usp(r16) // get new usp + + insll r13, 4, r13 // >> 32 +// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow + mtpr r14, pt_ptbr // load the new ptbr + + mtpr r13, cc // set new offset + ldqp r30, osfpcb_q_ksp(r16) // get new ksp + +// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow + mtpr r25, pt_usp // save usp + +#if ev5_p1 != 0 + + + blbc r8, no_pm_change // if monitoring all processes -- no need to change pm + + // otherwise, monitoring select processes - update pm + lda r25, 0x3F(r31) + cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings + + sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask + mfpr r22, ev5__pmctr + + and r8, r25, r8 // mask new ctl value + bic r22, r25, r22 // clear ctl field in pmctr + + or r8, r22, r8 + mtpr r8, ev5__pmctr + +no_pm_change: +#endif + + +#if osf_chm_fix != 0 + + + p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here + +#if build_fixed_image != 0 + + + hw_rei_stall +#else + + mfpr r9, pt_pcbb // get FEN +#endif + + ldqp r9, osfpcb_q_fen(r9) + blbc r9, no_pm_change_10_ // skip if FEN disabled + + mb // ensure no outstanding fills + lda r12, 1< + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + lda r17, mmcsr_c_acv(r31) // assume ACV + + stq r16, osfsf_pc(sp) // save pc + cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + ALIGN_BLOCK +//+ +//invalid_ipte_handler +// TNV detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R8 = pte +// R10 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch. +//- + +invalid_ipte_handler: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + nop + +invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + and r25, 1, r17 // Isolate kre + + stq r16, osfsf_pc(sp) // save pc + xor r17, 1, r17 // map to acv/tnv as a1 + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + + + + ALIGN_BLOCK +//+ +//invalid_dpte_handler +// INVALID detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R10 = va +// R8 = pte +// R9 = mm_stat +// PT6 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch +//- + + +invalid_dpte_handler: + mfpr r12, pt6 + blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode + + bis r12, r31, r14 // save PC in case of tbmiss or fault + srl r9, mm_stat_v_opcode, r25 // shift opc to <0> + + mtpr r11, pt0 // Save PS for stack write + and r25, mm_stat_m_opcode, r25 // isolate opcode + + cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M? + blbs r25, nmiss_fetch_ldr31_err // yes + + //dismiss exception if load to r31/f31 + blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits + + and r25, 0x1F, r25 // isolate rnum + nop + + cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31? + bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault + +invalid_dpte_no_dismiss: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r25 // Save va in case TBmiss on stack + and r9, 1, r13 // save r/w flag + + stq r16, osfsf_a0(sp) // a0 + or r25, r31, r16 // pass va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // assume acv + + srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0> + stq r29, osfsf_gp(sp) + + stq r18, osfsf_a2(sp) // a2 + cmovlbs r13, r25, r12 // if write access move acv based on write enable + + or r13, r31, r18 // pass flag of dstream access and read vs write + mfpr r25, pt0 // get ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r13, pt_entmm // get entry point + + stq r25, osfsf_ps(sp) // save ps + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv + + hw_rei_spe // out to exec + +//+ +// +// We come here if we are erring on a dtb_miss, and the instr is a +// fetch, fetch_m, of load to r31/f31. +// The PC is incremented, and we return to the program. +// essentially ignoring the instruction and error. +// +//- + ALIGN_BLOCK +nmiss_fetch_ldr31_err: + mfpr r12, pt6 + addq r12, 4, r12 // bump pc to pc+4 + + mtpr r12, exc_addr // and set entry point + mfpr r31, pt0 // pad exc_addr write + + hw_rei // + + ALIGN_BLOCK +//+ +// double_pte_inv +// We had a single tbmiss which turned into a double tbmiss which found +// an invalid PTE. Return to single miss with a fake pte, and the invalid +// single miss flow will report the error. +// +// on entry: +// r21 PTE +// r22 available +// VA IPR locked with original fault VA +// pt4 saved r21 +// pt5 saved r22 +// pt6 original exc_addr +// +// on return to tbmiss flow: +// r8 fake PTE +// +// +//- +double_pte_inv: + srl r21, osfpte_v_kre, r21 // get the kre bit to <0> + mfpr r22, exc_addr // get the pc + + lda r22, 4(r22) // inc the pc + lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set + + cmovlbc r21, r31, r8 // set to all 0 for acv if pte is 0 + mtpr r22, exc_addr // set for rei + + mfpr r21, pt4 // restore regs + mfpr r22, pt5 // restore regs + + hw_rei // back to tb miss + + ALIGN_BLOCK +//+ +//tnv_in_pal +// The only places in pal that ld or store are the +// stack builders, rti or retsys. Any of these mean we +// need to take a ksp not valid halt. +// +//- +tnv_in_pal: + + + br r31, ksp_inval_halt + + +// .sbttl "Icache flush routines" + + ALIGN_BLOCK +//+ +// Common Icache flush routine. +// +// +//- +pal_ic_flush: + nop + mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 + nop + nop + +// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 10 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 20 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 30 + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 40 + + nop + nop + +one_cycle_and_hw_rei: + nop + nop + + hw_rei_stall + +#if icflush_on_tbix != 0 + + + ALIGN_BLOCK + +//+ +// Common Icache flush and ITB invalidate single routine. +// ITBIS and hw_rei_stall must be in same octaword. +// r17 - has address to invalidate +// +//- +PAL_IC_FLUSH_AND_TBISI: + nop + mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 + nop + nop + +// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 10 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 20 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 30 + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 40 + + + nop + nop + + nop + nop + + // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions + // 44 nops plus 4 instructions before it is 48 instructions. + // Since this routine started on a 32-byte (8 instruction) boundary, + // the following 2 instructions will be in the same octword as required. +// ALIGN_BRANCH + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall + +#endif + + ALIGN_BLOCK +//+ +//osfpal_calpal_opcdec +// Here for all opcdec CALL_PALs +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +//- + +osfpal_calpal_opcdec: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + nop + + bis r11, r31, r12 // Save PS for stack write + bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +osfpal_calpal_opcdec_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + nop + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r17, osfsf_a1(sp) // a1 + + stq r14, osfsf_pc(sp) // save pc + nop + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + + + +//+ +//pal_update_pcb +// Update the PCB with the current SP, AST, and CC info +// +// r0 - return linkage +//- + ALIGN_BLOCK + +pal_update_pcb: + mfpr r12, pt_pcbb // get pcbb + and r11, osfps_m_mode, r25 // get mode + beq r25, pal_update_pcb_10_ // in kern? no need to update user sp + mtpr r30, pt_usp // save user stack + stqp r30, osfpcb_q_usp(r12) // store usp + br r31, pal_update_pcb_20_ // join common +pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp +pal_update_pcb_20_: rpcc r13 // get cyccounter + srl r13, 32, r14 // move offset + addl r13, r14, r14 // merge for new time + stlp r14, osfpcb_l_cc(r12) // save time + +//orig pvc_jsr updpcb, bsr=1, dest=1 + ret r31, (r0) + + + +#if remove_save_state == 0 + +// .sbttl "PAL_SAVE_STATE" +//+ +// +// Pal_save_state +// +// Function +// All chip state saved, all PT's, SR's FR's, IPR's +// +// +// Regs' on entry... +// +// R0 = halt code +// pt0 = r0 +// R1 = pointer to impure +// pt4 = r1 +// R3 = return addr +// pt5 = r3 +// +// register usage: +// r0 = halt_code +// r1 = addr of impure area +// r3 = return_address +// r4 = scratch +// +//- + + + ALIGN_BLOCK + .globl pal_save_state +pal_save_state: +// +// +// start of implementation independent save routine +// +// the impure area is larger than the addressibility of hw_ld and hw_st +// therefore, we need to play some games: The impure area +// is informally divided into the "machine independent" part and the +// "machine dependent" part. The state that will be saved in the +// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros). +// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros). +// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg +// macros will automagically adjust the offset correctly. +// + +// The distributed code is commented out and followed by corresponding SRC code. +// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0) + +//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area + lda r1, 0x200(r1) // Point to center of CPU segment +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag +//orig store_reg1 hlt, r0, r1, ipr=1 + SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code + + mfpr r0, pt0 // get r0 back //orig +//orig store_reg1 0, r0, r1 // save r0 + SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0 + + mfpr r0, pt4 // get r1 back //orig +//orig store_reg1 1, r0, r1 // save r1 + SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1 + +//orig store_reg 2 // save r2 + SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2 + + mfpr r0, pt5 // get r3 back //orig +//orig store_reg1 3, r0, r1 // save r3 + SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3 + + // reason code has been saved + // r0 has been saved + // r1 has been saved + // r2 has been saved + // r3 has been saved + // pt0, pt4, pt5 have been lost + + // + // Get out of shadow mode + // + + mfpr r2, icsr // Get icsr //orig +//orig ldah r0, <1@>(r31) // Get a one in SHADOW_ENABLE bit location + ldah r0, (1<<(icsr_v_sde-16))(r31) + bic r2, r0, r0 // ICSR with SDE clear //orig + mtpr r0, icsr // Turn off SDE //orig + + mfpr r31, pt0 // SDE bubble cycle 1 //orig + mfpr r31, pt0 // SDE bubble cycle 2 //orig + mfpr r31, pt0 // SDE bubble cycle 3 //orig + nop //orig + + + // save integer regs R4-r31 +//orig #define t 4 +//orig .repeat 28 +//orig store_reg \t +//orig #define t t + 1 +//orig .endr + SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) + SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) + SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) + SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) + SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) + SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) + SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) + SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) + SAVE_GPR(r12,CNS_Q_GPR+0x60,r1) + SAVE_GPR(r13,CNS_Q_GPR+0x68,r1) + SAVE_GPR(r14,CNS_Q_GPR+0x70,r1) + SAVE_GPR(r15,CNS_Q_GPR+0x78,r1) + SAVE_GPR(r16,CNS_Q_GPR+0x80,r1) + SAVE_GPR(r17,CNS_Q_GPR+0x88,r1) + SAVE_GPR(r18,CNS_Q_GPR+0x90,r1) + SAVE_GPR(r19,CNS_Q_GPR+0x98,r1) + SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1) + SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1) + SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1) + SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1) + SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1) + SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1) + SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1) + SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1) + SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1) + SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) + SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) + SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) + + // save all paltemp regs except pt0 + +//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores +//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores +//orig #define t 1 +//orig .repeat 23 +//orig store_reg \t , pal=1 +//orig #define t t + 1 +//orig .endr + + lda r1, -0x200(r1) // Restore the impure base address. + lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. + SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) + SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) + SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) + SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) + SAVE_IPR(pt5,CNS_Q_PT+0x28,r1) + SAVE_IPR(pt6,CNS_Q_PT+0x30,r1) + SAVE_IPR(pt7,CNS_Q_PT+0x38,r1) + SAVE_IPR(pt8,CNS_Q_PT+0x40,r1) + SAVE_IPR(pt9,CNS_Q_PT+0x48,r1) + SAVE_IPR(pt10,CNS_Q_PT+0x50,r1) + SAVE_IPR(pt11,CNS_Q_PT+0x58,r1) + SAVE_IPR(pt12,CNS_Q_PT+0x60,r1) + SAVE_IPR(pt13,CNS_Q_PT+0x68,r1) + SAVE_IPR(pt14,CNS_Q_PT+0x70,r1) + SAVE_IPR(pt15,CNS_Q_PT+0x78,r1) + SAVE_IPR(pt16,CNS_Q_PT+0x80,r1) + SAVE_IPR(pt17,CNS_Q_PT+0x88,r1) + SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) + SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) + SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) + SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) + SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) + SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + // Restore shadow mode + mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig + mfpr r31, pt0 //orig + mtpr r2, icsr // Restore original ICSR //orig + + mfpr r31, pt0 // SDE bubble cycle 1 //orig + mfpr r31, pt0 // SDE bubble cycle 2 //orig + mfpr r31, pt0 // SDE bubble cycle 3 //orig + nop //orig + + // save all integer shadow regs + +//orig #define t 8 +//orig .repeat 7 +//orig store_reg \t, shadow=1 +//orig #define t t + 1 +//orig .endr +//orig store_reg 25, shadow=1 + + SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + +//orig store_reg exc_addr, ipr=1 // save ipr +//orig store_reg pal_base, ipr=1 // save ipr +//orig store_reg mm_stat, ipr=1 // save ipr +//orig store_reg va, ipr=1 // save ipr +//orig store_reg icsr, ipr=1 // save ipr +//orig store_reg ipl, ipr=1 // save ipr +//orig store_reg ps, ipr=1 // save ipr +//orig store_reg itb_asn, ipr=1 // save ipr +//orig store_reg aster, ipr=1 // save ipr +//orig store_reg astrr, ipr=1 // save ipr +//orig store_reg sirr, ipr=1 // save ipr +//orig store_reg isr, ipr=1 // save ipr +//orig store_reg ivptbr, ipr=1 // save ipr +//orig store_reg mcsr, ipr=1 // save ipr +//orig store_reg dc_mode, ipr=1 // save ipr + + SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) + SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) + SAVE_IPR(va,CNS_Q_VA,r1) + SAVE_IPR(icsr,CNS_Q_ICSR,r1) + SAVE_IPR(ipl,CNS_Q_IPL,r1) + SAVE_IPR(ips,CNS_Q_IPS,r1) + SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + SAVE_IPR(aster,CNS_Q_ASTER,r1) + SAVE_IPR(astrr,CNS_Q_ASTRR,r1) + SAVE_IPR(sirr,CNS_Q_SIRR,r1) + SAVE_IPR(isr,CNS_Q_ISR,r1) + SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + SAVE_IPR(mcsr,CNS_Q_MCSR,r1) + SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1) + +//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st) +//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for +//orig // PVC violation applies only to +pvc$osf35$379: // loads. HW_ST ok here, so ignore + SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 + + + //the following iprs are informational only -- will not be restored + +//orig store_reg icperr_stat, ipr=1 +//orig store_reg pmctr, ipr=1 +//orig store_reg intid, ipr=1 +//orig store_reg exc_sum, ipr=1 +//orig store_reg exc_mask, ipr=1 +//orig ldah r14, 0xfff0(r31) +//orig zap r14, 0xE0, r14 // Get Cbox IPR base +//orig nop // pad mf dcperr_stat out of shadow of last store +//orig nop +//orig nop +//orig store_reg dcperr_stat, ipr=1 + + SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) + SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) + SAVE_IPR(intId,CNS_Q_INT_ID,r1) + SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) + SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) + ldah r14, 0xFFF0(zero) + zap r14, 0xE0, r14 // Get base address of CBOX IPRs + NOP // Pad mfpr dcPerr out of shadow of + NOP // last store + NOP + SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) + + // read cbox ipr state + +//orig mb +//orig ldqp r2, ev5__sc_ctl(r14) +//orig ldqp r13, ld_lock(r14) +//orig ldqp r4, ev5__sc_addr(r14) +//orig ldqp r5, ev5__ei_addr(r14) +//orig ldqp r6, ev5__bc_tag_addr(r14) +//orig ldqp r7, ev5__fill_syn(r14) +//orig bis r5, r4, r31 +//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them +//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr +//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn +//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked +//orig mb + +#ifndef SIMOS + mb + ldq_p r2, scCtl(r14) + ldq_p r13, ldLock(r14) + ldq_p r4, scAddr(r14) + ldq_p r5, eiAddr(r14) + ldq_p r6, bcTagAddr(r14) + ldq_p r7, fillSyn(r14) + bis r5, r4, zero // Make sure all loads complete before + bis r7, r6, zero // reading registers that unlock them. + ldq_p r8, scStat(r14) // Unlocks scAddr. + ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. + ldq_p zero, eiStat(r14) // Make sure it is really unlocked. + mb +#endif +//orig // save cbox ipr state +//orig store_reg1 sc_ctl, r2, r1, ipr=1 +//orig store_reg1 ld_lock, r13, r1, ipr=1 +//orig store_reg1 sc_addr, r4, r1, ipr=1 +//orig store_reg1 ei_addr, r5, r1, ipr=1 +//orig store_reg1 bc_tag_addr, r6, r1, ipr=1 +//orig store_reg1 fill_syn, r7, r1, ipr=1 +//orig store_reg1 sc_stat, r8, r1, ipr=1 +//orig store_reg1 ei_stat, r9, r1, ipr=1 +//orig //bc_config? sl_rcv? + + SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); + SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); + SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); + SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); + SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); + SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); + SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); + SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); + +// restore impure base //orig +//orig unfix_impure_ipr r1 + lda r1, -CNS_Q_IPR(r1) + +// save all floating regs //orig + mfpr r0, icsr // get icsr //orig + or r31, 1, r2 // get a one //orig +//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig + sll r2, icsr_v_fpe, r2 // Shift it into ICSR position + or r2, r0, r0 // set FEN on //orig + mtpr r0, icsr // write to icsr, enabling FEN //orig + +// map the save area virtually +// orig mtpr r31, dtb_ia // clear the dtb +// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA +// orig sll r0, 32, r0 // shift to PFN field +// orig lda r2, 0xff(r31) // all read enable and write enable bits set +// orig sll r2, 8, r2 // move to PTE location +// orig addq r0, r2, r0 // combine with PFN +// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit +// orig mtpr r1, dtb_tag // write TB tag + + mtpr r31, dtbIa // Clear all DTB entries + srl r1, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r1, dtbTag // Write the PTE and tag into the DTB + + +//orig // map the next page too - in case the impure area crosses a page boundary +//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page +//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA +//orig sll r0, 32, r0 // shift to PFN field +//orig lda r2, 0xff(r31) // all read enable and write enable bits set +//orig sll r2, 8, r2 // move to PTE location +//orig addq r0, r2, r0 // combine with PFN +//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit +//orig mtpr r4, dtb_tag // write TB tag + + lda r4, (1< // assertion checker +//orig or r31, <<1@> ! 1>, r2 // set SDE and FPE +//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot +//orig or r2, r0, r0 // set FEN on +//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr. + + mfpr r0, icsr // Get current ICSR + bis zero, 1, r2 // Get a '1' + or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 + sll r2, icsr_v_fpe, r2 // Shift bits into position + bis r2, r2, r0 // Set ICSR and ICSR + mtpr r0, icsr // Update the chip + + mfpr r31, pt0 // FPE bubble cycle 1 //orig + mfpr r31, pt0 // FPE bubble cycle 2 //orig + mfpr r31, pt0 // FPE bubble cycle 3 //orig + +//orig fix_impure_ipr r1 +//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 +//orig mt_fpcr f0 +//orig +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access +//orig +//orig // restore all floating regs +//orig#define t 0 +//orig .repeat 32 +//orig restore_reg \t , fpu=1 +//orig#define t t + 1 +//orig .endr + + lda r1, 200(r1) // Point to base of IPR area again + RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb + mt_fpcr f0 // original + + lda r1, 0x200(r1) // point to center of CPU segment + RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) + RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) + RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) + RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) + RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) + RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) + RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) + RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) + RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1) + RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1) + RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1) + RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1) + RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1) + RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1) + RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1) + RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1) + RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1) + RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1) + RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1) + RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1) + RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1) + RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1) + RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1) + RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1) + RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1) + RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) + RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) + RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) + RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) + RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) + RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) + RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) + +//orig // switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 +//orig +//orig // restore all pal regs +//orig#define t 1 +//orig .repeat 23 +//orig restore_reg \t , pal=1 +//orig#define t t + 1 +//orig .endr + + lda r1, -0x200(r1) // Restore base address of impure area. + lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. + RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) + RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) + RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) + RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) + RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) + RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) + RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) + RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1) + RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1) + RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1) + RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1) + RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1) + RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1) + RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1) + RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1) + RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1) + RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1) + RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1) + RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1) + RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1) + RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1) + RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1) + RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + +//orig restore_reg exc_addr, ipr=1 // restore ipr +//orig restore_reg pal_base, ipr=1 // restore ipr +//orig restore_reg ipl, ipr=1 // restore ipr +//orig restore_reg ps, ipr=1 // restore ipr +//orig mtpr r0, dtb_cm // set current mode in mbox too +//orig restore_reg itb_asn, ipr=1 +//orig srl r0, itb_asn_v_asn, r0 +//orig sll r0, dtb_asn_v_asn, r0 +//orig mtpr r0, dtb_asn // set ASN in Mbox too +//orig restore_reg ivptbr, ipr=1 +//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr +//orig restore_reg mcsr, ipr=1 +//orig restore_reg aster, ipr=1 +//orig restore_reg astrr, ipr=1 +//orig restore_reg sirr, ipr=1 +//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles +//orig mfpr r31, pt0 // (may issue with mt maf_mode) +//orig mfpr r31, pt0 // bubble cycle 1 +//orig mfpr r31, pt0 // bubble cycle 2 +//orig mfpr r31, pt0 // bubble cycle 3 +//orig mfpr r31, pt0 // (may issue with following ld) + + // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag) + RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1) + RESTORE_IPR(ipl,CNS_Q_IPL,r1) + RESTORE_IPR(ips,CNS_Q_IPS,r1) + mtpr r0, dtbCm // Set Mbox current mode too. + RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + srl r0, 4, r0 + sll r0, 57, r0 + mtpr r0, dtbAsn // Set Mbox ASN too + RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + mtpr r0, mVptBr // Set Mbox VptBr too + RESTORE_IPR(mcsr,CNS_Q_MCSR,r1) + RESTORE_IPR(aster,CNS_Q_ASTER,r1) + RESTORE_IPR(astrr,CNS_Q_ASTRR,r1) + RESTORE_IPR(sirr,CNS_Q_SIRR,r1) + RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1) + STALL + STALL + STALL + STALL + STALL + + + // restore all integer shadow regs +//orig#define t 8 +//orig .repeat 7 +//orig restore_reg \t, shadow=1 +//orig#define t t + 1 +//orig .endr +//orig restore_reg 25, shadow=1 +//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles + + RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) + + // + // Get out of shadow mode + // + + mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig + mfpr r31, pt0 // " //orig + mfpr r0, icsr // Get icsr //orig +//orig ldah r2, <1@>(r31) // Get a one in SHADOW_ENABLE bit location + ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig + bic r0, r2, r2 // ICSR with SDE clear //orig + mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig + + mfpr r31, pt0 // SDE bubble cycle 1 //orig + mfpr r31, pt0 // SDE bubble cycle 2 //orig + mfpr r31, pt0 // SDE bubble cycle 3 //orig + nop //orig + +//orig // switch impure pointer from ipr to gpr area -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 +//orig // restore all integer regs +//orig#define t 4 +//orig .repeat 28 +//orig restore_reg \t +//orig#define t t + 1 +//orig .endr + +// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... + + lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area + lda r1, 0x200(r1) // Point to center of CPU segment + + RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) + RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) + RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) + RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) + RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) + RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) + RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) + RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) + RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1) + RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1) + RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1) + RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1) + RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1) + RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1) + RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1) + RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1) + RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1) + RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1) + RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1) + RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1) + RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1) + RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1) + RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1) + RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1) + RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1) + RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1) + RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1) + RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1) + +//orig // switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 +//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei + + lda t0, -0x200(t0) // Restore base address of impure area. + lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again. + RESTORE_IPR(icsr,CNS_Q_ICSR,r1) + +//orig // and back again -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag +//orig mb + + lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again, + lda t0, 0x200(t0) // and back to center of CPU segment + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag + mb + +//orig // and back we go +//orig// restore_reg 3 +//orig restore_reg 2 +//orig// restore_reg 1 +//orig restore_reg 0 +//orig // restore impure area base +//orig unfix_impure_gpr r1 + + RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) + RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) + lda r1, -0x200(r1) // Restore impure base address + + mfpr r31, pt0 // stall for ldqp above //orig + + mtpr r31, dtb_ia // clear the tb //orig + mtpr r31, itb_ia // clear the itb //orig + +//orig pvc_jsr rststa, bsr=1, dest=1 + ret r31, (r3) // back we go //orig +#endif + + +//+ +// pal_pal_bug_check -- code has found a bugcheck situation. +// Set things up and join common machine check flow. +// +// Input: +// r14 - exc_addr +// +// On exit: +// pt0 - saved r0 +// pt1 - saved r1 +// pt4 - saved r4 +// pt5 - saved r5 +// pt6 - saved r6 +// pt10 - saved exc_addr +// pt_misc<47:32> - mchk code +// pt_misc<31:16> - scb vector +// r14 - base of Cbox IPRs in IO space +// MCES is set +//- + + ALIGN_BLOCK + .globl pal_pal_bug_check_from_int +pal_pal_bug_check_from_int: + DEBUGSTORE(0x79) +//simos DEBUG_EXC_ADDR() + DEBUGSTORE(0x20) +//simos bsr r25, put_hex + lda r25, mchk_c_bugcheck(r31) + addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed + br r31, pal_pal_mchk + nop + +pal_pal_bug_check: + lda r25, mchk_c_bugcheck(r31) + +pal_pal_mchk: + sll r25, 32, r25 // Move mchk code to position + + mtpr r14, pt10 // Stash exc_addr + mtpr r14, exc_addr + + mfpr r12, pt_misc // Get MCES and scratch + zap r12, 0x3c, r12 + + or r12, r25, r12 // Combine mchk code + lda r25, scb_v_procmchk(r31) // Get SCB vector + + sll r25, 16, r25 // Move SCBv to position + or r12, r25, r25 // Combine SCBv + + mtpr r0, pt0 // Stash for scratch + bis r25, mces_m_mchk, r25 // Set MCES bit + + mtpr r25, pt_misc // Save mchk code!scbv!whami!mces + ldah r14, 0xfff0(r31) + + mtpr r1, pt1 // Stash for scratch + zap r14, 0xE0, r14 // Get Cbox IPR base + + mtpr r4, pt4 + mtpr r5, pt5 + + mtpr r6, pt6 + blbs r12, sys_double_machine_check // MCHK halt if double machine check + + br r31, sys_mchk_collect_iprs // Join common machine check flow + +// align_to_call_pal_section // Align to address of first call_pal entry point - 2000 + +// .sbttl "HALT - PALcode for HALT instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// GO to console code +// +//- + + .text 1 +// . = 0x2000 + CALL_PAL_PRIV(PAL_HALT_ENTRY) +call_pal_halt: +#if rax_mode == 0 + mfpr r31, pt0 // Pad exc_addr read + mfpr r31, pt0 + + mfpr r12, exc_addr // get PC + subq r12, 4, r12 // Point to the HALT + + mtpr r12, exc_addr + mtpr r0, pt0 + +//orig pvc_jsr updpcb, bsr=1 + bsr r0, pal_update_pcb // update the pcb + lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt + br r31, sys_enter_console // enter the console + +#else // RAX mode + mb + mb + mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles. + mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles. + mtpr r8, exc_addr // no HW_REI for 1 cycle. + blbc r9, not_begin_case + mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles. + mtpr r31, ev5__itb_ia // clear ITB. + +not_begin_case: + nop + nop + + nop + nop // pad mt itb_asn ->hw_rei_stall + + hw_rei_stall +#endif + +// .sbttl "CFLUSH- PALcode for CFLUSH instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// R16 - contains the PFN of the page to be flushed +// +// Function: +// Flush all Dstream caches of 1 entire page +// The CFLUSH routine is in the system specific module. +// +//- + + CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) +Call_Pal_Cflush: + br r31, sys_cflush + +// .sbttl "DRAINA - PALcode for DRAINA instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Implicit TRAPB performed by hardware. +// +// Function: +// Stall instruction issue until all prior instructions are guaranteed to +// complete without incurring aborts. For the EV5 implementation, this +// means waiting until all pending DREADS are returned. +// +//- + + CALL_PAL_PRIV(PAL_DRAINA_ENTRY) +Call_Pal_Draina: + ldah r14, 0x100(r31) // Init counter. Value? + nop + +DRAINA_LOOP: + subq r14, 1, r14 // Decrement counter + mfpr r13, ev5__maf_mode // Fetch status bit + + srl r13, maf_mode_v_dread_pending, r13 + ble r14, DRAINA_LOOP_TOO_LONG + + nop + blbs r13, DRAINA_LOOP // Wait until all DREADS clear + + hw_rei + +DRAINA_LOOP_TOO_LONG: + br r31, call_pal_halt + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x0003) +CallPal_OpcDec03: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0004) +CallPal_OpcDec04: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0005) +CallPal_OpcDec05: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0006) +CallPal_OpcDec06: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0007) +CallPal_OpcDec07: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0008) +CallPal_OpcDec08: + br r31, osfpal_calpal_opcdec + +// .sbttl "CSERVE- PALcode for CSERVE instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Various functions for private use of console software +// +// option selector in r0 +// arguments in r16.... +// The CSERVE routine is in the system specific module. +// +//- + + CALL_PAL_PRIV(PAL_CSERVE_ENTRY) +Call_Pal_Cserve: + br r31, sys_cserve + +// .sbttl "swppal - PALcode for swppal instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Vectored into via hardware PALcode instruction dispatch. +// R16 contains the new PAL identifier +// R17:R21 contain implementation-specific entry parameters +// +// R0 receives status: +// 0 success (PAL was switched) +// 1 unknown PAL variant +// 2 known PAL variant, but PAL not loaded +// +// +// Function: +// Swap control to another PAL. +//- + + CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) +Call_Pal_Swppal: + cmpule r16, 255, r0 // see if a kibble was passed + cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) + + or r16, r31, r3 // set r3 incase this is a address + blbc r0, swppal_cont // nope, try it as an address + + cmpeq r16, 2, r0 // is it our friend OSF? + blbc r0, swppal_fail // nope, don't know this fellow + + br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF + +// .global osfpal_hw_entry_reset +// .weak osfpal_hw_entry_reset +// .long +//orig halt // don't know how to get the address here - kludge ok, load pal at 0 + .long 0 // ?? hack upon hack...pb + +CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr +// ble r3, swppal_fail ; if OSF not linked in say not loaded. + mfpr r2, pal_base // fetch pal base + + addq r2, r3, r3 // add pal base + lda r2, 0x3FFF(r31) // get pal base checker mask + + and r3, r2, r2 // any funky bits set? + cmpeq r2, 0, r0 // + + blbc r0, swppal_fail // return unknown if bad bit set. + br r31, swppal_cont + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000B) +CallPal_OpcDec0B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000C) +CallPal_OpcDec0C: + br r31, osfpal_calpal_opcdec + +// .sbttl "wripir- PALcode for wripir instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// r16 = processor number to interrupt +// +// Function: +// IPIR <- R16 +// Handled in system-specific code +// +// Exit: +// interprocessor interrupt is recorded on the target processor +// and is initiated when the proper enabling conditions are present. +//- + + CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) +Call_Pal_Wrpir: + br r31, sys_wripir + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000E) +CallPal_OpcDec0E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000F) +CallPal_OpcDec0F: + br r31, osfpal_calpal_opcdec + +// .sbttl "rdmces- PALcode for rdmces instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// R0 <- ZEXT(MCES) +//- + + CALL_PAL_PRIV(PAL_RDMCES_ENTRY) +Call_Pal_Rdmces: + mfpr r0, pt_mces // Read from PALtemp + and r0, mces_m_all, r0 // Clear other bits + + hw_rei + +// .sbttl "wrmces- PALcode for wrmces instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) +// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) +// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) +// MCES<3> <- R16<3> (DPC) +// MCES<4> <- R16<4> (DSC) +// +//- + + CALL_PAL_PRIV(PAL_WRMCES_ENTRY) +Call_Pal_Wrmces: + and r16, ((1<read restriction +#else + blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock +#endif + + nop + hw_rei + + + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x0012) +CallPal_OpcDec12: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0013) +CallPal_OpcDec13: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0014) +CallPal_OpcDec14: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0015) +CallPal_OpcDec15: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0016) +CallPal_OpcDec16: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0017) +CallPal_OpcDec17: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0018) +CallPal_OpcDec18: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0019) +CallPal_OpcDec19: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001A) +CallPal_OpcDec1A: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001B) +CallPal_OpcDec1B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001C) +CallPal_OpcDec1C: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001D) +CallPal_OpcDec1D: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001E) +CallPal_OpcDec1E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001F) +CallPal_OpcDec1F: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0020) +CallPal_OpcDec20: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0021) +CallPal_OpcDec21: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0022) +CallPal_OpcDec22: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0023) +CallPal_OpcDec23: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0024) +CallPal_OpcDec24: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0025) +CallPal_OpcDec25: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0026) +CallPal_OpcDec26: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0027) +CallPal_OpcDec27: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0028) +CallPal_OpcDec28: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0029) +CallPal_OpcDec29: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002A) +CallPal_OpcDec2A: + br r31, osfpal_calpal_opcdec + +// .sbttl "wrfen - PALcode for wrfen instruction" + +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// a0<0> -> ICSR +// Store new FEN in PCB +// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE +// +// Issue: What about pending FP loads when FEN goes from on->off???? +//- + + CALL_PAL_PRIV(PAL_WRFEN_ENTRY) +Call_Pal_Wrfen: + or r31, 1, r13 // Get a one + mfpr r1, ev5__icsr // Get current FPE + + sll r13, icsr_v_fpe, r13 // shift 1 to icsr spot, e0 + and r16, 1, r16 // clean new fen + + sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position + bic r1, r13, r1 // zero icsr + + or r1, r12, r1 // Or new FEN into ICSR + mfpr r12, pt_pcbb // Get PCBB - E1 + + mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI + stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB. + + mfpr r31, pt0 // Pad ICSR write. + mfpr r31, pt0 + + mfpr r31, pt0 +// pvc_violate 225 // cuz PVC can't distinguish which bits changed + hw_rei + + + CALL_PAL_PRIV(0x002C) +CallPal_OpcDec2C: + br r31, osfpal_calpal_opcdec + +// .sbttl "wrvptpr - PALcode for wrvptpr instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// vptptr <- a0 (r16) +//- + + CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) +Call_Pal_Wrvptptr: + mtpr r16, ev5__mvptbr // Load Mbox copy + mtpr r16, ev5__ivptbr // Load Ibox copy + nop // Pad IPR write + nop + hw_rei + + CALL_PAL_PRIV(0x002E) +CallPal_OpcDec2E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002F) +CallPal_OpcDec2F: + br r31, osfpal_calpal_opcdec + +// .sbttl "swpctx- PALcode for swpctx instruction" + +//+ +// +// Entry: +// hardware dispatch via callPal instruction +// R16 -> new pcb +// +// Function: +// dynamic state moved to old pcb +// new state loaded from new pcb +// pcbb pointer set +// old pcbb returned in R0 +// +// Note: need to add perf monitor stuff +//- + + CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) +Call_Pal_Swpctx: + rpcc r13 // get cyccounter + mfpr r0, pt_pcbb // get pcbb + + ldqp r22, osfpcb_q_fen(r16) // get new fen/pme + ldqp r23, osfpcb_l_cc(r16) // get new asn + + srl r13, 32, r25 // move offset + mfpr r24, pt_usp // get usp + + stqp r30, osfpcb_q_ksp(r0) // store old ksp +// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow. + mtpr r16, pt_pcbb // set new pcbb + + stqp r24, osfpcb_q_usp(r0) // store usp + addl r13, r25, r25 // merge for new time + + stlp r25, osfpcb_l_cc(r0) // save time + ldah r24, (1<<(icsr_v_fpe-16))(r31) + + and r22, 1, r12 // isolate fen + mfpr r25, icsr // get current icsr + + ev5_pass2 lda r24, (1< +// PS <- a0<2:0> (r16) +// +// t8 (r22) is scratch +//- + + CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) +Call_Pal_Swpipl: + and r16, osfps_m_ipl, r16 // clean New ipl + mfpr r22, pt_intmask // get int mask + + extbl r22, r16, r22 // get mask for this ipl + bis r11, r31, r0 // return old ipl + + bis r16, r31, r11 // set new ps + mtpr r22, ev5__ipl // set new mask + + mfpr r31, pt0 // pad ipl write + mfpr r31, pt0 // pad ipl write + + hw_rei // back + +// .sbttl "rdps - PALcode for rdps instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- ps +//- + + CALL_PAL_PRIV(PAL_RDPS_ENTRY) +Call_Pal_Rdps: + bis r11, r31, r0 // Fetch PALshadow PS + nop // Must be 2 cycles long + hw_rei + +// .sbttl "wrkgp - PALcode for wrkgp instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// kgp <- a0 (r16) +//- + + CALL_PAL_PRIV(PAL_WRKGP_ENTRY) +Call_Pal_Wrkgp: + nop + mtpr r16, pt_kgp + nop // Pad for pt write->read restriction + nop + hw_rei + +// .sbttl "wrusp - PALcode for wrusp instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// usp <- a0 (r16) +//- + + CALL_PAL_PRIV(PAL_WRUSP_ENTRY) +Call_Pal_Wrusp: + nop + mtpr r16, pt_usp + nop // Pad possible pt write->read restriction + nop + hw_rei + +// .sbttl "wrperfmon - PALcode for wrperfmon instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// +// Function: +// Various control functions for the onchip performance counters +// +// option selector in r16 +// option argument in r17 +// returned status in r0 +// +// +// r16 = 0 Disable performance monitoring for one or more cpu's +// r17 = 0 disable no counters +// r17 = bitmask disable counters specified in bit mask (1=disable) +// +// r16 = 1 Enable performance monitoring for one or more cpu's +// r17 = 0 enable no counters +// r17 = bitmask enable counters specified in bit mask (1=enable) +// +// r16 = 2 Mux select for one or more cpu's +// r17 = Mux selection (cpu specific) +// <24:19> bc_ctl field (see spec) +// <31>,<7:4>,<3:0> pmctr ,, fields (see spec) +// +// r16 = 3 Options +// r17 = (cpu specific) +// <0> = 0 log all processes +// <0> = 1 log only selected processes +// <30,9,8> mode select - ku,kp,kk +// +// r16 = 4 Interrupt frequency select +// r17 = (cpu specific) indicates interrupt frequencies desired for each +// counter, with "zero interrupts" being an option +// frequency info in r17 bits as defined by PMCTR_CTL below +// +// r16 = 5 Read Counters +// r17 = na +// r0 = value (same format as ev5 pmctr) +// <0> = 0 Read failed +// <0> = 1 Read succeeded +// +// r16 = 6 Write Counters +// r17 = value (same format as ev5 pmctr; all counters written simultaneously) +// +// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0 +// r17 = 0 enable no counters +// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear) +// +//============================================================================= +//Assumptions: +//PMCTR_CTL: +// +// <15:14> CTL0 -- encoded frequency select and enable - CTR0 +// <13:12> CTL1 -- " - CTR1 +// <11:10> CTL2 -- " - CTR2 +// +// <9:8> FRQ0 -- frequency select for CTR0 (no enable info) +// <7:6> FRQ1 -- frequency select for CTR1 +// <5:4> FRQ2 -- frequency select for CTR2 +// +// <0> all vs. select processes (0=all,1=select) +// +// where +// FRQx<1:0> +// 0 1 disable interrupt +// 1 0 frequency = 65536 (16384 for ctr2) +// 1 1 frequency = 256 +// note: FRQx<1:0> = 00 will keep counters from ever being enabled. +// +//============================================================================= +// + CALL_PAL_PRIV(0x0039) +// unsupported in Hudson code .. pboyle Nov/95 +CALL_PAL_Wrperfmon: +#if perfmon_debug == 0 + // "real" performance monitoring code + cmpeq r16, 1, r0 // check for enable + bne r0, perfmon_en // br if requested to enable + + cmpeq r16, 2, r0 // check for mux ctl + bne r0, perfmon_muxctl // br if request to set mux controls + + cmpeq r16, 3, r0 // check for options + bne r0, perfmon_ctl // br if request to set options + + cmpeq r16, 4, r0 // check for interrupt frequency select + bne r0, perfmon_freq // br if request to change frequency select + + cmpeq r16, 5, r0 // check for counter read request + bne r0, perfmon_rd // br if request to read counters + + cmpeq r16, 6, r0 // check for counter write request + bne r0, perfmon_wr // br if request to write counters + + cmpeq r16, 7, r0 // check for counter clear/enable request + bne r0, perfmon_enclr // br if request to clear/enable counters + + beq r16, perfmon_dis // br if requested to disable (r16=0) + br r31, perfmon_unknown // br if unknown request +#else + + br r31, pal_perfmon_debug +#endif + +// .sbttl "rdusp - PALcode for rdusp instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- usp +//- + + CALL_PAL_PRIV(PAL_RDUSP_ENTRY) +Call_Pal_Rdusp: + nop + mfpr r0, pt_usp + hw_rei + + + CALL_PAL_PRIV(0x003B) +CallPal_OpcDec3B: + br r31, osfpal_calpal_opcdec + +// .sbttl "whami - PALcode for whami instruction" +//+ +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- whami +//- + CALL_PAL_PRIV(PAL_WHAMI_ENTRY) +Call_Pal_Whami: + nop + mfpr r0, pt_whami // Get Whami + extbl r0, 1, r0 // Isolate just whami bits + hw_rei + +// .sbttl "retsys - PALcode for retsys instruction" +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// 00(sp) contains return pc +// 08(sp) contains r29 +// +// Function: +// Return from system call. +// mode switched from kern to user. +// stacks swapped, ugp, upc restored. +// r23, r25 junked +//- + + CALL_PAL_PRIV(PAL_RETSYS_ENTRY) +Call_Pal_Retsys: + lda r25, osfsf_c_size(sp) // pop stack + bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr + + mfpr r14, exc_addr // save exc_addr in case of fault + ldq r23, osfsf_pc(sp) // get pc + + ldq r29, osfsf_gp(sp) // get gp + stl_c r31, -4(sp) // clear lock_flag + + lda r11, 1<