From c4898b15bcf5458e35f17cb0c3b4185cec0081aa Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 31 Jan 2013 07:49:14 -0500 Subject: mem: Add DDR3 and LPDDR2 DRAM controller configurations This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration. --- tests/configs/o3-timing-checker.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/configs/o3-timing-checker.py') diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py index a33a2ac06..cd15cf66b 100644 --- a/tests/configs/o3-timing-checker.py +++ b/tests/configs/o3-timing-checker.py @@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), cpu.clock = '2GHz' system = System(cpu = cpu, - physmem = SimpleDRAM(), + physmem = SimpleDDR3(), membus = CoherentBus(), mem_mode = "timing") system.system_port = system.membus.slave -- cgit v1.2.3