From 651de2d9af8ac628b69b40812ff036231da40ae3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 26 Oct 2012 06:42:42 -0400 Subject: config: Fix the cache class naming in regression scripts This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts. --- tests/configs/o3-timing-mp.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests/configs/o3-timing-mp.py') diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 2b611fb9d..6f3bddc6f 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -39,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -47,8 +47,8 @@ system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: - cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache -- cgit v1.2.3