From 6fc0094337bc0356c55232c3850fb5fd2dab1f0c Mon Sep 17 00:00:00 2001 From: Mrinmoy Ghosh Date: Tue, 25 Sep 2012 11:49:41 -0500 Subject: Cache: add a response latency to the caches In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path. --- tests/configs/pc-o3-timing.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'tests/configs/pc-o3-timing.py') diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index 2d3019daf..c3e705705 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -39,7 +39,8 @@ mem_size = '128MB' # ==================== class L1(BaseCache): - latency = '1ns' + hit_latency = '1ns' + response_latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -51,7 +52,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = '10ns' + hit_latency = '10ns' + response_latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,7 +64,8 @@ class L2(BaseCache): class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - latency = '1ns' + hit_latency = '1ns' + response_latency = '1ns' mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -73,7 +76,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - latency = '50ns' + hit_latency = '50ns' + response_latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 -- cgit v1.2.3