From d22796c03cba79307eac6a332cede20ca88f57cc Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 25 Oct 2012 04:32:44 -0400 Subject: config: Use shared cache config for regressions This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch. The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions. As only regressions that shared the same cache configuration are updated, no regressions are affected. --- tests/configs/pc-simple-timing.py | 54 ++------------------------------------- 1 file changed, 2 insertions(+), 52 deletions(-) (limited to 'tests/configs/pc-simple-timing.py') diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index bfbf926dc..990179008 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -31,60 +31,10 @@ from m5.objects import * m5.util.addToPath('../configs/common') from Benchmarks import SysConfig import FSConfig - +from Caches import * mem_size = '128MB' -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 4 - tgts_per_mshr = 8 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 - -# --------------------- -# Page table walker cache -# --------------------- -class PageTableWalkerCache(BaseCache): - assoc = 2 - block_size = 64 - hit_latency = 2 - response_latency = 2 - mshrs = 10 - size = '1kB' - tgts_per_mshr = 12 - -# --------------------- -# I/O Cache -# --------------------- -class IOCache(BaseCache): - assoc = 8 - block_size = 64 - hit_latency = 50 - response_latency = 50 - mshrs = 20 - size = '1kB' - tgts_per_mshr = 12 - addr_ranges = [AddrRange(0, size=mem_size)] - forward_snoops = False - #cpu cpu = TimingSimpleCPU(cpu_id=0) #the system @@ -95,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache -system.iocache = IOCache(clock = '1GHz') +system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave -- cgit v1.2.3