From 3cf733bcc07b0a8bf069f8581b7f3902bc38f0e0 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:07:09 -0400 Subject: Regression: Use addTwoLevelCacheHierarchy in configs This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache. --- tests/configs/realview-o3-checker.py | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) (limited to 'tests/configs/realview-o3-checker.py') diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py index 56990eb54..961a4a698 100644 --- a/tests/configs/realview-o3-checker.py +++ b/tests/configs/realview-o3-checker.py @@ -85,26 +85,23 @@ cpu = DerivO3CPU(cpu_id=0) system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu -#create the l1/l2 bus -system.toL2Bus = CoherentBus() +#connect up the checker +cpu.addCheckerCpu() + +#create the iocache system.iocache = IOCache() system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave - -#connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the checker -cpu.addCheckerCpu() -#connect up the cpu and l1s +#connect up the cpu and caches +cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4), + L2(size = '4MB', assoc = 8)) +# create the interrupt controller cpu.createInterruptController() -cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) -# connect cpu level-1 caches to shared level-2 cache -cpu.connectAllPorts(system.toL2Bus, system.membus) +# connect cpu and caches to the rest of the system +cpu.connectAllPorts(system.membus) +# set the cpu clock along with the caches and l1-l2 bus cpu.clock = '2GHz' root = Root(full_system=True, system=system) -- cgit v1.2.3