From 5a9a743cfc4517f93e5c94533efa767b92272c59 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 13 Feb 2012 06:43:09 -0500 Subject: MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. --- tests/configs/realview-simple-timing-dual.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tests/configs/realview-simple-timing-dual.py') diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 95daa81b6..e55cb72cb 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -72,8 +72,8 @@ cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus @@ -81,8 +81,8 @@ system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: -- cgit v1.2.3