From 4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 18 Aug 2006 00:16:23 -0400 Subject: Add caches in, fix cpu.mem param --HG-- extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c --- tests/configs/simple-timing.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'tests/configs/simple-timing.py') diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 8be0c0b3b..9a5b20e88 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -37,8 +37,9 @@ class MyCache(BaseCache): tgts_per_mshr = 5 cpu = TimingSimpleCPU() -#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), -# MyCache(size = '2MB')) +cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), + MyCache(size = '2MB')) +cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), -- cgit v1.2.3