From d22796c03cba79307eac6a332cede20ca88f57cc Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 25 Oct 2012 04:32:44 -0400 Subject: config: Use shared cache config for regressions This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch. The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions. As only regressions that shared the same cache configuration are updated, no regressions are affected. --- tests/configs/tsunami-o3-dual.py | 43 ++-------------------------------------- 1 file changed, 2 insertions(+), 41 deletions(-) (limited to 'tests/configs/tsunami-o3-dual.py') diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 5ba14753d..a1564f8f8 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -30,46 +30,7 @@ import m5 from m5.objects import * m5.util.addToPath('../configs/common') import FSConfig - - -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 4 - tgts_per_mshr = 20 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 - -# --------------------- -# I/O Cache -# --------------------- -class IOCache(BaseCache): - assoc = 8 - block_size = 64 - hit_latency = 50 - response_latency = 50 - mshrs = 20 - size = '1kB' - tgts_per_mshr = 12 - addr_ranges = [AddrRange(0, size='8GB')] - forward_snoops = False - is_top_level = True +from Caches import * #cpu cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] @@ -79,7 +40,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus #create the l1/l2 bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.iocache = IOCache(clock = '1GHz') +system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave -- cgit v1.2.3