From 6629d9b2bc58a885bfebce1517fd12483497b6e4 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Jul 2008 11:10:33 -0700 Subject: mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. --- tests/configs/tsunami-simple-atomic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/configs/tsunami-simple-atomic.py') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 2374734ec..0c6feaeac 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -62,8 +62,8 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - mem_side_filter_ranges=[AddrRange(0, Addr.max)] - cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + addr_range=AddrRange(0, size='8GB') + forward_snoops = False #cpu cpu = AtomicSimpleCPU(cpu_id=0) -- cgit v1.2.3