From a432d8e0851de8d090676697e29ca6ed4be64fb7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 17 Mar 2011 19:20:19 -0500 Subject: Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. --- tests/configs/tsunami-simple-timing-dual.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tests/configs/tsunami-simple-timing-dual.py') diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index f0105461d..747cdac18 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -40,6 +40,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache @@ -64,6 +65,7 @@ class IOCache(BaseCache): tgts_per_mshr = 12 addr_range=AddrRange(0, size='8GB') forward_snoops = False + is_top_level = True #cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] -- cgit v1.2.3