From f32f372455c99bf5765f5fda3efc7da180dfcda8 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 7 Jan 2013 13:05:33 -0500 Subject: tests: Create base classes to encapsulate common test configurations Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration. The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation. * BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations. * BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible. Architecture specific implementations are provided for ARM, Alpha, and X86. --- tests/configs/tsunami-simple-timing-dual.py | 51 ++++++++--------------------- 1 file changed, 14 insertions(+), 37 deletions(-) (limited to 'tests/configs/tsunami-simple-timing-dual.py') diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 4d74d9057..2ca280f06 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,42 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') - +from alpha_generic import * +root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU, + num_cpus=2).create_root() -- cgit v1.2.3