From 9493501fdb087c82111d8692995474f2e8f3f390 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 10 Aug 2007 16:14:02 -0400 Subject: Regression: Add an I/O Cache to the full system regressions that have a cache. --HG-- extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176 --- tests/configs/tsunami-simple-timing.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'tests/configs/tsunami-simple-timing.py') diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 3f18c6848..96cd27111 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -53,6 +53,19 @@ class L2(BaseCache): tgts_per_mshr = 16 write_buffers = 8 +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + mem_side_filter_ranges=[AddrRange(0, Addr.max)] + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] + #cpu cpu = TimingSimpleCPU(cpu_id=0) #the system @@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -- cgit v1.2.3