From 1f6d5f8f849f50a3646f586b1274708537124ef3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sat, 20 Sep 2014 17:18:32 -0400 Subject: mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh --- tests/configs/base_config.py | 4 ++-- tests/configs/memtest-filter.py | 8 ++++---- tests/configs/memtest-ruby.py | 2 +- tests/configs/memtest.py | 6 +++--- tests/configs/o3-timing-mp-ruby.py | 2 +- tests/configs/o3-timing-ruby.py | 2 +- tests/configs/simple-atomic-mp-ruby.py | 2 +- tests/configs/tgen-dram-ctrl.py | 2 +- tests/configs/tgen-simple-mem.py | 2 +- 9 files changed, 15 insertions(+), 15 deletions(-) (limited to 'tests/configs') diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index e9487546d..ccf1ea6f8 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -102,7 +102,7 @@ class BaseSystem(object): Returns: A bus that CPUs should use to connect to the shared cache. """ - system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) + system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain) system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master @@ -184,7 +184,7 @@ class BaseSESystem(BaseSystem): def create_system(self): system = System(physmem = self.mem_class(), - membus = CoherentBus(), + membus = CoherentXBar(), mem_mode = self.mem_mode) system.system_port = system.membus.slave system.physmem.port = system.membus.master diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index 4de009d76..35d64a793 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -37,9 +37,9 @@ cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), + funcbus = NoncoherentXBar(), physmem = SimpleMemory(), - membus = CoherentBus(width=16, snoop_filter = SnoopFilter())) + membus = CoherentXBar(width=16, snoop_filter = SnoopFilter())) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', @@ -50,8 +50,8 @@ system.clk_domain = SrcClockDomain(clock = '1GHz', system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) -system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16, - snoop_filter = SnoopFilter()) +system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16, + snoop_filter = SnoopFilter()) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 071f3a7b5..08b73cd2f 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -81,7 +81,7 @@ options.num_cpus = nb_cores system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), physmem = SimpleMemory(null = True), - funcbus = NoncoherentBus()) + funcbus = NoncoherentXBar()) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index fbd18b779..e1bdc64fa 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -37,9 +37,9 @@ cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), + funcbus = NoncoherentXBar(), physmem = SimpleMemory(), - membus = CoherentBus(width=16)) + membus = CoherentXBar(width=16)) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', @@ -50,7 +50,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz', system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) -system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) +system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index 292c7a42d..3fea4ed71 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -38,7 +38,7 @@ import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated -system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), +system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(), mem_mode = "timing", clk_domain = SrcClockDomain(clock = '1GHz')) diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index d1b471bac..68a07e702 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -39,7 +39,7 @@ cpu = DerivO3CPU(cpu_id=0) system = System(cpu = cpu, physmem = ruby_memory, - membus = CoherentBus(), + membus = CoherentXBar(), mem_mode = "timing", clk_domain = SrcClockDomain(clock = '1GHz')) diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 9feccb12c..321cb977f 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -38,7 +38,7 @@ import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated -system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), +system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(), clk_domain = SrcClockDomain(clock = '1GHz')) # Create a seperate clock domain for components that should run at diff --git a/tests/configs/tgen-dram-ctrl.py b/tests/configs/tgen-dram-ctrl.py index c98b92650..d170ac077 100644 --- a/tests/configs/tgen-dram-ctrl.py +++ b/tests/configs/tgen-dram-ctrl.py @@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-dram-ctrl.cfg") # system simulated system = System(cpu = cpu, physmem = DDR3_1600_x64(), - membus = NoncoherentBus(width = 16), + membus = NoncoherentXBar(width = 16), clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = VoltageDomain())) diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py index 7fdeb9c12..1e07efe2c 100644 --- a/tests/configs/tgen-simple-mem.py +++ b/tests/configs/tgen-simple-mem.py @@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") # system simulated system = System(cpu = cpu, physmem = SimpleMemory(), - membus = NoncoherentBus(width = 16), + membus = NoncoherentXBar(width = 16), clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = VoltageDomain())) -- cgit v1.2.3