From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- tests/configs/memtest.py | 4 +-- tests/configs/o3-timing-mp.py | 4 +-- tests/configs/o3-timing.py | 2 +- tests/configs/simple-atomic-mp.py | 4 +-- tests/configs/simple-timing-mp.py | 4 +-- tests/configs/simple-timing.py | 4 +-- tests/configs/tsunami-simple-atomic-dual.py | 43 ++++++++++++++++++++++++++-- tests/configs/tsunami-simple-atomic.py | 43 ++++++++++++++++++++++++++-- tests/configs/tsunami-simple-timing-dual.py | 44 +++++++++++++++++++++++++++-- tests/configs/tsunami-simple-timing.py | 44 +++++++++++++++++++++++++++-- 10 files changed, 176 insertions(+), 20 deletions(-) (limited to 'tests/configs') diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..15a4f8f05 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1e414294c..1ac9bd2e4 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,7 +35,7 @@ m5.AddToPath('../configs/common') # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,7 +47,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d20a7e0c8..366a3eb0d 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,7 +33,7 @@ m5.AddToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index e8000cd0a..de0793d1c 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index a263bcf57..1fd0e8c3c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 6c4b8232f..0ed985a17 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -32,13 +32,13 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) + MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 7ed854f44..131095055 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,12 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) - -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 4859f30cf..595b1aeda 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,10 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = AtomicSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 0c8c3d523..47fba30ff 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,11 +31,51 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + + diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + -- cgit v1.2.3