From ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 19 Aug 2011 15:08:09 -0500 Subject: ARM: Add some MP regressions and clean up the disk images and kernels a bit --- tests/configs/realview-o3-dual.py | 101 +++++++++++++++++++++++++++ tests/configs/realview-o3.py | 4 +- tests/configs/realview-simple-atomic-dual.py | 101 +++++++++++++++++++++++++++ tests/configs/realview-simple-atomic.py | 4 +- tests/configs/realview-simple-timing-dual.py | 101 +++++++++++++++++++++++++++ tests/configs/realview-simple-timing.py | 4 +- 6 files changed, 309 insertions(+), 6 deletions(-) create mode 100644 tests/configs/realview-o3-dual.py create mode 100644 tests/configs/realview-simple-atomic-dual.py create mode 100644 tests/configs/realview-simple-timing-dual.py (limited to 'tests/configs') diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py new file mode 100644 index 000000000..1718a76e8 --- /dev/null +++ b/tests/configs/realview-o3-dual.py @@ -0,0 +1,101 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') +import FSConfig +from Benchmarks import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + is_top_level = True + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + addr_range=AddrRange(0, size='256MB') + forward_snoops = False + +#cpu +cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] +#the system +system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + +system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port +system.l2c.num_cpus = 2 + +#connect up the cpu and l1s +for c in cpus: + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectAllPorts(system.toL2Bus, system.membus) + c.clock = '2GHz' + + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 2d805fe0a..89f320c04 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -64,7 +64,7 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - addr_range=AddrRange(0, size='128MB') + addr_range=AddrRange(0, size='256MB') forward_snoops = False #cpu @@ -76,7 +76,7 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py new file mode 100644 index 000000000..b301eac14 --- /dev/null +++ b/tests/configs/realview-simple-atomic-dual.py @@ -0,0 +1,101 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') +import FSConfig +from Benchmarks import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + is_top_level = True + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + addr_range=AddrRange(0, size='256MB') + forward_snoops = False + +#cpu +cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system +system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + +system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port +system.l2c.num_cpus = 2 + +#connect up the cpu and l1s +for c in cpus: + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectAllPorts(system.toL2Bus, system.membus) + c.clock = '2GHz' + + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index 7340be7a4..b74e56073 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -63,7 +63,7 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - addr_range=AddrRange(0, size='128MB') + addr_range=AddrRange(0, size='256MB') forward_snoops = False #cpu @@ -71,7 +71,7 @@ cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py new file mode 100644 index 000000000..1f1402dfc --- /dev/null +++ b/tests/configs/realview-simple-timing-dual.py @@ -0,0 +1,101 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') +import FSConfig +from Benchmarks import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + is_top_level = True + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + addr_range=AddrRange(0, size='256MB') + forward_snoops = False + +#cpu +cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system +system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) +system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.port +system.iocache.mem_side = system.membus.port + +system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port +system.l2c.num_cpus = 2 + +#connect up the cpu and l1s +for c in cpus: + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectAllPorts(system.toL2Bus, system.membus) + c.clock = '2GHz' + + +root = Root(system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 83b643c52..74fc617f3 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -64,7 +64,7 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - addr_range=AddrRange(0, size='128MB') + addr_range=AddrRange(0, size='256MB') forward_snoops = False #cpu @@ -76,7 +76,7 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port -- cgit v1.2.3