From f85286b3debf4a4a94d3b959e5bb880be81bd692 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:08 -0600 Subject: MEM: Add port proxies instead of non-structural ports Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh --- tests/configs/inorder-timing.py | 1 + tests/configs/memtest-ruby.py | 4 ++++ tests/configs/memtest.py | 2 ++ tests/configs/o3-timing-mp.py | 2 ++ tests/configs/o3-timing.py | 1 + tests/configs/rubytest-ruby.py | 3 +++ tests/configs/simple-atomic-mp.py | 2 ++ tests/configs/simple-atomic.py | 1 + tests/configs/simple-timing-mp-ruby.py | 3 +++ tests/configs/simple-timing-mp.py | 2 ++ tests/configs/simple-timing-ruby.py | 3 +++ tests/configs/simple-timing.py | 1 + 12 files changed, 25 insertions(+) (limited to 'tests/configs') diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index ddf37b5ec..1bab83609 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -50,6 +50,7 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 49f152017..2517e7670 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -109,6 +109,10 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.access_phys_mem = False + +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f62381473..66e49a63e 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -76,6 +76,8 @@ for cpu in cpus: cpu.l1c.mem_side = system.toL2Bus.port system.funcmem.port = cpu.functional +system.system_port = system.membus.port + # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 9f7c89c7b..67aaebd21 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -79,6 +79,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# connect system port to membus +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index fec21c177..395fd24a3 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -50,6 +50,7 @@ cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index b63833ccf..a7e598b0a 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -105,6 +105,9 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.access_phys_mem = False +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index 4db741b8a..e722ef334 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -78,6 +78,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# connect system port to membus +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index 4a2efcc57..191230164 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -32,6 +32,7 @@ from m5.objects import * system = System(cpu = AtomicSimpleCPU(cpu_id=0), physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port system.cpu.connectAllPorts(system.membus) system.cpu.clock = '2GHz' diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index d57ccea15..58ca862e1 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -88,6 +88,9 @@ for (i, cpu) in enumerate(system.cpu): cpu.icache_port = system.ruby._cpu_ruby_ports[i].port cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 6f4090ec2..f1ebb1939 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -75,6 +75,8 @@ for cpu in cpus: cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' +system.system_port = system.membus.port + # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 1d67f6f97..359421a49 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,6 +85,9 @@ assert(len(system.ruby._cpu_ruby_ports) == 1) cpu.icache_port = system.ruby._cpu_ruby_ports[0].port cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_port_proxy.port + # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index bc9d016c5..cc0d1d207 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -46,6 +46,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) +system.system_port = system.membus.port system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) cpu.clock = '2GHz' -- cgit v1.2.3 From 2208ea049f60618e432c69c065926bcbc810581a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:09 -0600 Subject: MEM: Make the bus bridge unidirectional and fixed address range This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time. --- tests/configs/pc-o3-timing.py | 2 -- tests/configs/pc-simple-atomic.py | 2 -- tests/configs/pc-simple-timing.py | 2 -- tests/configs/realview-o3-dual.py | 2 -- tests/configs/realview-o3.py | 2 -- tests/configs/realview-simple-atomic-dual.py | 2 -- tests/configs/realview-simple-atomic.py | 2 -- tests/configs/realview-simple-timing-dual.py | 2 -- tests/configs/realview-simple-timing.py | 2 -- tests/configs/tsunami-inorder.py | 2 -- tests/configs/tsunami-o3-dual.py | 2 -- tests/configs/tsunami-o3.py | 2 -- tests/configs/tsunami-simple-atomic-dual.py | 2 -- tests/configs/tsunami-simple-atomic.py | 2 -- tests/configs/tsunami-simple-timing-dual.py | 2 -- tests/configs/tsunami-simple-timing.py | 2 -- tests/configs/twosys-tsunami-simple-atomic.py | 11 +++++++++++ 17 files changed, 11 insertions(+), 32 deletions(-) (limited to 'tests/configs') diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index c697e97a9..0fe23d1ee 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -86,8 +86,6 @@ cpu = DerivO3CPU(cpu_id=0) mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') -system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] -system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] system.iocache = IOCache(addr_range=mem_size) system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index 1c35ff2d9..eeff17069 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -88,8 +88,6 @@ cpu = AtomicSimpleCPU(cpu_id=0) mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') -system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] -system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] system.iocache = IOCache(addr_range=mem_size) system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 9c9f4aeca..a1b2f4676 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -91,8 +91,6 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] -system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] system.iocache = IOCache(addr_range=mem_size) system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index 489b5c5b6..69c583abd 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 61e7591e6..bab5a193d 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -75,8 +75,6 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py index b301eac14..edfd940ad 100644 --- a/tests/configs/realview-simple-atomic-dual.py +++ b/tests/configs/realview-simple-atomic-dual.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index b74e56073..83f85641a 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -70,8 +70,6 @@ class IOCache(BaseCache): cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 1f1402dfc..7fe0d409b 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 74fc617f3..90f2539e6 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -75,8 +75,6 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py index fd62e252a..a08261533 100644 --- a/tests/configs/tsunami-inorder.py +++ b/tests/configs/tsunami-inorder.py @@ -79,8 +79,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 786452a09..c63637f73 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -76,8 +76,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index 8a003dad8..a6bb4b122 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -76,8 +76,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 2e56ce851..758dbef09 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('atomic') -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 3c1981464..a2335d763 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeLinuxAlphaSystem('atomic') -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 747cdac18..ad466a5c0 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -71,8 +71,6 @@ class IOCache(BaseCache): cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('timing') -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 110e6ee74..7dc0ded5c 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -76,8 +76,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index 7c6fde7c3..658508fa0 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -36,11 +36,22 @@ test_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-stream-client.rcS')) test_sys.cpu = AtomicSimpleCPU(cpu_id=0) test_sys.cpu.connectAllPorts(test_sys.membus) +# In contrast to the other (one-system) Tsunami configurations we do +# not have an IO cache but instead rely on an IO bridge for accesses +# from masters on the IO bus to the memory bus +test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [AddrRange(0, '8GB')]) +test_sys.iobridge.slave = test_sys.iobus.port +test_sys.iobridge.master = test_sys.membus.port drive_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-server.rcS')) drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) drive_sys.cpu.connectAllPorts(drive_sys.membus) +drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [AddrRange(0, '8GB')]) +drive_sys.iobridge.slave = drive_sys.iobus.port +drive_sys.iobridge.master = drive_sys.membus.port root = makeDualRoot(test_sys, drive_sys, "ethertrace") -- cgit v1.2.3