From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 25 Jan 2012 17:19:50 +0000 Subject: stats: Update stats for final tick and memory bandwidth patches --- tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini') diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 50ef6266f..0bc5277c7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -146,7 +149,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -164,7 +167,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -188,7 +191,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -198,5 +201,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] -- cgit v1.2.3