From 272d867402e50dba49f1f78976711388a8056427 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 28 Sep 2007 13:22:34 -0400 Subject: Update statistics for the last three revisions --HG-- extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24 --- tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing') diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index b76b4e6c1..9e54c6441 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1730291 # Simulator instruction rate (inst/s) -host_mem_usage 181616 # Number of bytes of host memory used -host_seconds 347.84 # Real time elapsed on the host -host_tick_rate 2208778962 # Simulator tick rate (ticks/s) +host_inst_rate 1400395 # Simulator instruction rate (inst/s) +host_mem_usage 199872 # Number of bytes of host memory used +host_seconds 429.78 # Real time elapsed on the host +host_tick_rate 1787654853 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.768293 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 52084 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 768292872000 # number of cpu cycles simulated +system.cpu.numCycles 1536585744 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls -- cgit v1.2.3