From 57e07ac2d2daaa7469241372510395e43ebe14c0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Jan 2012 07:24:45 -0800 Subject: SE/FS: Make both SE and FS tests available all the time. --HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => 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=> tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : 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=> tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => 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tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : 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=> tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : 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=> tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : 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tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => 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tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => 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tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => 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tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py --- .../ref/alpha/tru64/inorder-timing/config.ini | 240 --------- .../00.gzip/ref/alpha/tru64/inorder-timing/simerr | 6 - .../00.gzip/ref/alpha/tru64/inorder-timing/simout | 42 -- .../ref/alpha/tru64/inorder-timing/stats.txt | 315 ------------ .../00.gzip/ref/alpha/tru64/o3-timing/config.ini | 535 --------------------- .../long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 6 - .../long/00.gzip/ref/alpha/tru64/o3-timing/simout | 42 -- .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 517 -------------------- .../ref/alpha/tru64/simple-atomic/config.ini | 102 ---- .../00.gzip/ref/alpha/tru64/simple-atomic/simerr | 6 - .../00.gzip/ref/alpha/tru64/simple-atomic/simout | 42 -- .../ref/alpha/tru64/simple-atomic/stats.txt | 77 --- .../ref/alpha/tru64/simple-timing/config.ini | 205 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tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout delete mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt delete mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini delete mode 100755 tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr delete mode 100755 tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout delete mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt (limited to 'tests/long/00.gzip/ref/alpha') diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini deleted file mode 100644 index 6c1c0e974..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ /dev/null @@ -1,240 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -activity=0 -cachePorts=2 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -cpu_id=0 -dataMemPort=dcache_port -defer_registration=false -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchBuffSize=4 -fetchMemPort=icache_port -functionTrace=false -functionTraceStart=0 -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -stageTracing=false -stageWidth=4 -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout deleted file mode 100755 index 30b31a527..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ /dev/null @@ -1,42 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 274500333500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt deleted file mode 100644 index b5662ac02..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ /dev/null @@ -1,315 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.274500 # Number of seconds simulated -sim_ticks 274500333500 # Number of ticks simulated -final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113367 # Simulator instruction rate (inst/s) -host_tick_rate 51705325 # Simulator tick rate (ticks/s) -host_mem_usage 207980 # Number of bytes of host memory used -host_seconds 5308.94 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -system.physmem.bytes_read 5894016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798080 # Number of bytes written to this memory -system.physmem.num_reads 92094 # Number of read requests responded to by this memory -system.physmem.num_writes 59345 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39666597 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668899 # DTB write accesses -system.cpu.dtb.data_hits 154184165 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189098 # DTB accesses -system.cpu.itb.fetch_hits 27986226 # ITB hits -system.cpu.itb.fetch_misses 22 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 27986248 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 549000668 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. -system.cpu.activity 89.164571 # Percentage of cycles cpu is active -system.cpu.comLoads 114514042 # Number of Load instructions committed -system.cpu.comStores 39451321 # Number of Store instructions committed -system.cpu.comBranches 62547159 # Number of Branches instructions committed -system.cpu.comNops 36304520 # Number of Nop instructions committed -system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed -system.cpu.comInts 349039879 # Number of Integer instructions committed -system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads -system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154582342 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use -system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses -system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394244 # number of overall hits -system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408188 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73797 # number of replacements -system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364156 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92094 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59345 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index cc9b0c683..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index ad1c408b1..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,42 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 144450185500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 8681db468..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,517 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.144450 # Number of seconds simulated -sim_ticks 144450185500 # Number of ticks simulated -final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205040 # Simulator instruction rate (inst/s) -host_tick_rate 52370107 # Simulator tick rate (ticks/s) -host_mem_usage 208620 # Number of bytes of host memory used -host_seconds 2758.26 # Real time elapsed on the host -sim_insts 565552443 # Number of instructions simulated -system.physmem.bytes_read 5936768 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797120 # Number of bytes written to this memory -system.physmem.num_reads 92762 # Number of read requests responded to by this memory -system.physmem.num_writes 59330 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125584378 # DTB read hits -system.cpu.dtb.read_misses 26780 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125611158 # DTB read accesses -system.cpu.dtb.write_hits 41433696 # DTB write hits -system.cpu.dtb.write_misses 32002 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41465698 # DTB write accesses -system.cpu.dtb.data_hits 167018074 # DTB hits -system.cpu.dtb.data_misses 58782 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167076856 # DTB accesses -system.cpu.itb.fetch_hits 70952399 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 70952439 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 288900372 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued -system.cpu.iq.rate 2.148217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45034525 # number of nop insts executed -system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed -system.cpu.iew.exec_branches 68658345 # Number of branches executed -system.cpu.iew.exec_stores 41485194 # Number of stores executed -system.cpu.iew.exec_rate 2.122282 # Inst execution rate -system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420036286 # num instructions producing a value -system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle -system.cpu.commit.count 601856963 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 153965363 # Number of memory references committed -system.cpu.commit.loads 114514042 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 62547159 # Number of branches committed -system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. -system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. -system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 935932678 # The number of ROB reads -system.cpu.rob.rob_writes 1385724156 # The number of ROB writes -system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 565552443 # Number of Instructions Simulated -system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads -system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 863490102 # number of integer regfile reads -system.cpu.int_regfile_writes 500818441 # number of integer regfile writes -system.cpu.fp_regfile_reads 272 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use -system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses -system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470690 # number of replacements -system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use -system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74463 # number of replacements -system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 382968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92762 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59330 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 282141772..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 1dc402141..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,42 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 300930958000 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index ad4f39b85..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.300931 # Number of seconds simulated -sim_ticks 300930958000 # Number of ticks simulated -final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4527143 # Simulator instruction rate (inst/s) -host_tick_rate 2263589972 # Simulator tick rate (ticks/s) -host_mem_usage 198960 # Number of bytes of host memory used -host_seconds 132.94 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -system.physmem.bytes_read 2782990928 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_written 152669504 # Number of bytes written to this memory -system.physmem.num_reads 716375939 # Number of read requests responded to by this memory -system.physmem.num_writes 39451321 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.data_hits 153965363 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153970296 # DTB accesses -system.cpu.itb.fetch_hits 601861897 # ITB hits -system.cpu.itb.fetch_misses 20 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 601861917 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 601861917 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses -system.cpu.num_func_calls 2395217 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls -system.cpu.num_int_insts 563959696 # number of integer instructions -system.cpu.num_fp_insts 1520 # number of float instructions -system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read -system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written -system.cpu.num_fp_register_reads 169 # number of times the floating registers were read -system.cpu.num_fp_register_writes 42 # number of times the floating registers were written -system.cpu.num_mem_refs 153970296 # number of memory refs -system.cpu.num_load_insts 114516673 # Number of load instructions -system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 601861917 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 0bc5277c7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 36bd68fb7..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,42 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 765623032000 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 4d7850adf..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,266 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.765623 # Number of seconds simulated -sim_ticks 765623032000 # Number of ticks simulated -final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2199350 # Simulator instruction rate (inst/s) -host_tick_rate 2797795440 # Simulator tick rate (ticks/s) -host_mem_usage 207676 # Number of bytes of host memory used -host_seconds 273.65 # Real time elapsed on the host -sim_insts 601856964 # Number of instructions simulated -system.physmem.bytes_read 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797824 # Number of bytes written to this memory -system.physmem.num_reads 92031 # Number of read requests responded to by this memory -system.physmem.num_writes 59341 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.data_hits 153965363 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153970296 # DTB accesses -system.cpu.itb.fetch_hits 601861898 # ITB hits -system.cpu.itb.fetch_misses 20 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 601861918 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1531246064 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses -system.cpu.num_func_calls 2395217 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls -system.cpu.num_int_insts 563959696 # number of integer instructions -system.cpu.num_fp_insts 1520 # number of float instructions -system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read -system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written -system.cpu.num_fp_register_reads 169 # number of times the floating registers were read -system.cpu.num_fp_register_writes 42 # number of times the floating registers were written -system.cpu.num_mem_refs 153970296 # number of memory refs -system.cpu.num_load_insts 114516673 # Number of load instructions -system.cpu.num_store_insts 39453623 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1531246064 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use -system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use -system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408190 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73734 # number of replacements -system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59341 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- -- cgit v1.2.3