From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 25 Jan 2012 17:19:50 +0000 Subject: stats: Update stats for final tick and memory bandwidth patches --- .../00.gzip/ref/alpha/tru64/inorder-timing/config.ini | 10 ++++++---- .../00.gzip/ref/alpha/tru64/inorder-timing/simout | 6 +++--- .../00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 19 +++++++++++++++---- .../long/00.gzip/ref/alpha/tru64/o3-timing/config.ini | 8 +++++--- tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 6 ++---- .../long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 19 +++++++++++++++---- .../00.gzip/ref/alpha/tru64/simple-atomic/config.ini | 13 ++++++++----- .../long/00.gzip/ref/alpha/tru64/simple-atomic/simout | 8 ++++---- .../00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 19 +++++++++++++++---- .../00.gzip/ref/alpha/tru64/simple-timing/config.ini | 11 +++++++---- .../long/00.gzip/ref/alpha/tru64/simple-timing/simout | 8 ++++---- .../00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 19 +++++++++++++++---- 12 files changed, 99 insertions(+), 47 deletions(-) (limited to 'tests/long/00.gzip/ref/alpha') diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index b6c1d1a1d..6c1c0e974 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=InOrderCPU @@ -182,7 +184,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -205,7 +207,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -224,7 +226,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -234,5 +236,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 9da502021..30b31a527 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 16:09:24 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:24:12 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index ec1428295..b5662ac02 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.274500 # Number of seconds simulated sim_ticks 274500333500 # Number of ticks simulated +final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56944 # Simulator instruction rate (inst/s) -host_tick_rate 25971361 # Simulator tick rate (ticks/s) -host_mem_usage 245756 # Number of bytes of host memory used -host_seconds 10569.35 # Real time elapsed on the host +host_inst_rate 113367 # Simulator instruction rate (inst/s) +host_tick_rate 51705325 # Simulator tick rate (ticks/s) +host_mem_usage 207980 # Number of bytes of host memory used +host_seconds 5308.94 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +system.physmem.bytes_read 5894016 # Number of bytes read from this memory +system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3798080 # Number of bytes written to this memory +system.physmem.num_reads 92094 # Number of read requests responded to by this memory +system.physmem.num_writes 59345 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index b11fadb7f..cc9b0c683 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 9acd0ed7e..ad1c408b1 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 16:10:02 -gem5 started Aug 20 2011 16:10:09 +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:24:12 gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index bcb696265..8681db468 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.144450 # Number of seconds simulated sim_ticks 144450185500 # Number of ticks simulated +final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180758 # Simulator instruction rate (inst/s) -host_tick_rate 46168195 # Simulator tick rate (ticks/s) -host_mem_usage 205240 # Number of bytes of host memory used -host_seconds 3128.78 # Real time elapsed on the host +host_inst_rate 205040 # Simulator instruction rate (inst/s) +host_tick_rate 52370107 # Simulator tick rate (ticks/s) +host_mem_usage 208620 # Number of bytes of host memory used +host_seconds 2758.26 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated +system.physmem.bytes_read 5936768 # Number of bytes read from this memory +system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3797120 # Number of bytes written to this memory +system.physmem.num_reads 92762 # Number of read requests responded to by this memory +system.physmem.num_writes 59330 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 355960d42..282141772 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaTLB @@ -61,7 +64,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 7ce6e1e9f..1dc402141 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 12:20:39 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:24:12 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index b2d2b0068..ad4f39b85 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.300931 # Number of seconds simulated sim_ticks 300930958000 # Number of ticks simulated +final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3663682 # Simulator instruction rate (inst/s) -host_tick_rate 1831855621 # Simulator tick rate (ticks/s) -host_mem_usage 184012 # Number of bytes of host memory used -host_seconds 164.28 # Real time elapsed on the host +host_inst_rate 4527143 # Simulator instruction rate (inst/s) +host_tick_rate 2263589972 # Simulator tick rate (ticks/s) +host_mem_usage 198960 # Number of bytes of host memory used +host_seconds 132.94 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +system.physmem.bytes_read 2782990928 # Number of bytes read from this memory +system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_written 152669504 # Number of bytes written to this memory +system.physmem.num_reads 716375939 # Number of read requests responded to by this memory +system.physmem.num_writes 39451321 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 50ef6266f..0bc5277c7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -146,7 +149,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -164,7 +167,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -188,7 +191,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -198,5 +201,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 26ae974dd..36bd68fb7 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 12:47:45 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:24:12 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 9bcf790a8..4d7850adf 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.765623 # Number of seconds simulated sim_ticks 765623032000 # Number of ticks simulated +final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1640067 # Simulator instruction rate (inst/s) -host_tick_rate 2086331180 # Simulator tick rate (ticks/s) -host_mem_usage 192652 # Number of bytes of host memory used -host_seconds 366.97 # Real time elapsed on the host +host_inst_rate 2199350 # Simulator instruction rate (inst/s) +host_tick_rate 2797795440 # Simulator tick rate (ticks/s) +host_mem_usage 207676 # Number of bytes of host memory used +host_seconds 273.65 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +system.physmem.bytes_read 5889984 # Number of bytes read from this memory +system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3797824 # Number of bytes written to this memory +system.physmem.num_reads 92031 # Number of read requests responded to by this memory +system.physmem.num_writes 59341 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv -- cgit v1.2.3