From 1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 27 Jul 2010 01:03:44 -0400 Subject: ARM: Add regression tests --- .../00.gzip/ref/arm/linux/simple-atomic/stats.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt (limited to 'tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt') diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..f2e408360 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2670640 # Simulator instruction rate (inst/s) +host_mem_usage 197140 # Number of bytes of host memory used +host_seconds 223.66 # Real time elapsed on the host +host_tick_rate 1335369827 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 597325393 # Number of instructions simulated +sim_seconds 0.298674 # Number of seconds simulated +sim_ticks 298674141000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 597348283 # number of cpu cycles simulated +system.cpu.num_insts 597325393 # Number of instructions executed +system.cpu.num_refs 219174038 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- -- cgit v1.2.3