From 0622eec53ae87e008a8d5e0e685321c69ea401d3 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 24 Jul 2008 16:31:54 -0700 Subject: regress: update regressions for tty emulation fix. --- .../ref/sparc/linux/simple-timing/m5stats.txt | 244 ++++++++++----------- 1 file changed, 122 insertions(+), 122 deletions(-) (limited to 'tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt') diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 49a7103b2..db0a24071 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1554729 # Simulator instruction rate (inst/s) -host_mem_usage 223840 # Number of bytes of host memory used -host_seconds 958.05 # Real time elapsed on the host -host_tick_rate 2160793398 # Simulator tick rate (ticks/s) +host_inst_rate 2417575 # Simulator instruction rate (inst/s) +host_mem_usage 214112 # Number of bytes of host memory used +host_seconds 616.12 # Real time elapsed on the host +host_tick_rate 3359990664 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070158 # Number of seconds simulated -sim_ticks 2070157841000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.070168 # Number of seconds simulated +sim_ticks 2070168106000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16193.228451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13193.228451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3133163000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2552705000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency @@ -28,50 +28,50 @@ system.cpu.dcache.SwapReq_misses 40 # nu system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 8629063000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7670278000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22924.696101 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 11762226000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10222983000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22924.696101 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 11762226000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513071 # number of overall misses +system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10222983000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,57 +83,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449114 # number of replacements -system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316430 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4095.496088 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 375475000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316420 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26953.026197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.026197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29837000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 26516000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26953.026197 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 29837000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26516000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26953.026197 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles +system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_miss_latency 29837000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_misses 1107 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26516000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -145,78 +145,78 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 115 # number of replacements -system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use -system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.562887 # Cycle average of tags in use +system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5973905000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857085000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 776158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 371206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232053 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1377654000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658900000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316430 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.429642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6750063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3228181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3228291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160837 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293471 # number of overall misses +system.cpu.l2cache.overall_hits 160847 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6750063000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293481 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3228181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3228291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,17 +228,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82889 # number of replacements -system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82905 # number of replacements +system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16362.166769 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61877 # number of writebacks +system.cpu.l2cache.writebacks 61861 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4140315682 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 4140336212 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3