From 19273164da50011d59b7f362026f8e80260807d4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 8 Dec 2008 07:16:40 -0800 Subject: output: Change default output directory and files and update tests. --HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt --- .../00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt | 449 --------------------- .../long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 2 + .../long/00.gzip/ref/alpha/tru64/o3-timing/simout | 46 +++ .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 449 +++++++++++++++++++++ .../long/00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 - .../long/00.gzip/ref/alpha/tru64/o3-timing/stdout | 46 --- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 34 -- .../00.gzip/ref/alpha/tru64/simple-atomic/simerr | 2 + .../00.gzip/ref/alpha/tru64/simple-atomic/simout | 46 +++ .../ref/alpha/tru64/simple-atomic/stats.txt | 34 ++ .../00.gzip/ref/alpha/tru64/simple-atomic/stderr | 2 - .../00.gzip/ref/alpha/tru64/simple-atomic/stdout | 46 --- .../ref/alpha/tru64/simple-timing/m5stats.txt | 250 ------------ .../00.gzip/ref/alpha/tru64/simple-timing/simerr | 2 + .../00.gzip/ref/alpha/tru64/simple-timing/simout | 46 +++ .../ref/alpha/tru64/simple-timing/stats.txt | 250 ++++++++++++ .../00.gzip/ref/alpha/tru64/simple-timing/stderr | 2 - .../00.gzip/ref/alpha/tru64/simple-timing/stdout | 46 --- .../00.gzip/ref/sparc/linux/o3-timing/m5stats.txt | 439 -------------------- .../long/00.gzip/ref/sparc/linux/o3-timing/simerr | 2 + .../long/00.gzip/ref/sparc/linux/o3-timing/simout | 47 +++ .../00.gzip/ref/sparc/linux/o3-timing/stats.txt | 439 ++++++++++++++++++++ .../long/00.gzip/ref/sparc/linux/o3-timing/stderr | 2 - .../long/00.gzip/ref/sparc/linux/o3-timing/stdout | 47 --- .../ref/sparc/linux/simple-atomic/m5stats.txt | 18 - .../00.gzip/ref/sparc/linux/simple-atomic/simerr | 2 + .../00.gzip/ref/sparc/linux/simple-atomic/simout | 47 +++ .../ref/sparc/linux/simple-atomic/stats.txt | 18 + .../00.gzip/ref/sparc/linux/simple-atomic/stderr | 2 - .../00.gzip/ref/sparc/linux/simple-atomic/stdout | 47 --- .../ref/sparc/linux/simple-timing/m5stats.txt | 244 ----------- .../00.gzip/ref/sparc/linux/simple-timing/simerr | 2 + .../00.gzip/ref/sparc/linux/simple-timing/simout | 47 +++ .../ref/sparc/linux/simple-timing/stats.txt | 244 +++++++++++ .../00.gzip/ref/sparc/linux/simple-timing/stderr | 2 - .../00.gzip/ref/sparc/linux/simple-timing/stdout | 47 --- .../ref/x86/linux/simple-atomic/m5stats.txt | 18 - .../00.gzip/ref/x86/linux/simple-atomic/simerr | 9 + .../00.gzip/ref/x86/linux/simple-atomic/simout | 47 +++ .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 18 + .../00.gzip/ref/x86/linux/simple-atomic/stderr | 9 - .../00.gzip/ref/x86/linux/simple-atomic/stdout | 47 --- .../ref/x86/linux/simple-timing/m5stats.txt | 234 ----------- .../00.gzip/ref/x86/linux/simple-timing/simerr | 9 + .../00.gzip/ref/x86/linux/simple-timing/simout | 47 +++ .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 234 +++++++++++ .../00.gzip/ref/x86/linux/simple-timing/stderr | 9 - .../00.gzip/ref/x86/linux/simple-timing/stdout | 47 --- 48 files changed, 2089 insertions(+), 2089 deletions(-) delete mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt create mode 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr create mode 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout create mode 100644 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt delete mode 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr delete mode 100755 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout delete mode 100644 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt create mode 100755 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr create mode 100755 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tests/long/00.gzip/ref/x86/linux/simple-timing/stdout (limited to 'tests/long/00.gzip/ref') diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 4e08b47b3..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718859 # Number of BTB hits -global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -global.BPredUnit.lookups 76039018 # Number of BP lookups -global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 193677 # Simulator instruction rate (inst/s) -host_mem_usage 202220 # Number of bytes of host memory used -host_seconds 2920.07 # Real time elapsed on the host -host_tick_rate 57217081 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078146500 # Number of ticks simulated -system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711249 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088757 3349.40% - 1 100475751 3113.49% - 2 37367184 1157.91% - 3 9733028 301.60% - 4 10676883 330.85% - 5 22147835 686.31% - 6 13251874 410.64% - 7 3269687 101.32% - 8 17700250 548.49% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:loads 115049510 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 154862033 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit -system.cpu.committedInsts 565552443 # Number of Instructions Simulated -system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415339 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182768 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468828 # number of replacements -system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 163077390 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 163013880 # DTB hits -system.cpu.dtb.misses 63510 # DTB misses -system.cpu.dtb.read_accesses 122284109 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260496 # DTB read hits -system.cpu.dtb.read_misses 23613 # DTB read misses -system.cpu.dtb.write_accesses 40793281 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40753384 # DTB write hits -system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581112 -system.cpu.fetch.rateDist.min_value 0 - 0 201466223 6057.66% - 1 10360747 311.53% - 2 15882081 477.54% - 3 14599006 438.96% - 4 12362950 371.73% - 5 14822134 445.67% - 6 6008311 180.66% - 7 3307530 99.45% - 8 53772130 1616.81% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013237 # number of overall hits -system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1169 # number of overall misses -system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use -system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316859 # Number of branches executed -system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41189464 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value -system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375802 # num instructions producing a value -system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle -system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834840 72.45% # Type of FU issued - IntMult 6546 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 29 0.00% # Type of FU issued - FloatCmp 5 0.00% # Type of FU issued - FloatCvt 5 0.00% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855453 20.61% # Type of FU issued - MemWrite 42021230 6.94% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390831 74.54% # attempts to use FU when none available - IntMult 67 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 1490139 20.60% # attempts to use FU when none available - MemWrite 351286 4.86% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92203773 2772.37% - 1 67051353 2016.09% - 2 80133780 2409.45% - 3 36043478 1083.75% - 4 30084945 904.59% - 5 14579095 438.36% - 6 10850493 326.25% - 7 1143008 34.37% - 8 491187 14.77% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 66014446 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 66014406 # ITB hits -system.cpu.itb.misses 40 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292443 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 85262 # number of replacements -system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.numCycles 334156294 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..4ea4c0572 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:25:12 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..4e08b47b3 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 65718859 # Number of BTB hits +global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups +global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted +global.BPredUnit.lookups 76039018 # Number of BP lookups +global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. +host_inst_rate 193677 # Simulator instruction rate (inst/s) +host_mem_usage 202220 # Number of bytes of host memory used +host_seconds 2920.07 # Real time elapsed on the host +host_tick_rate 57217081 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 565552443 # Number of instructions simulated +sim_seconds 0.167078 # Number of seconds simulated +sim_ticks 167078146500 # Number of ticks simulated +system.cpu.commit.COM:branches 62547159 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 322711249 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 108088757 3349.40% + 1 100475751 3113.49% + 2 37367184 1157.91% + 3 9733028 301.60% + 4 10676883 330.85% + 5 22147835 686.31% + 6 13251874 410.64% + 7 3269687 101.32% + 8 17700250 548.49% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:loads 115049510 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 154862033 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit +system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated +system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 149415339 # number of overall hits +system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3182768 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 468828 # number of replacements +system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use +system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334123 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 163077390 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 163013880 # DTB hits +system.cpu.dtb.misses 63510 # DTB misses +system.cpu.dtb.read_accesses 122284109 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 122260496 # DTB read hits +system.cpu.dtb.read_misses 23613 # DTB read misses +system.cpu.dtb.write_accesses 40793281 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 40753384 # DTB write hits +system.cpu.dtb.write_misses 39897 # DTB write misses +system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched +system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 332581112 +system.cpu.fetch.rateDist.min_value 0 + 0 201466223 6057.66% + 1 10360747 311.53% + 2 15882081 477.54% + 3 14599006 438.96% + 4 12362950 371.73% + 5 14822134 445.67% + 6 6008311 180.66% + 7 3307530 99.45% + 8 53772130 1616.81% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 66013237 # number of overall hits +system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_misses 1169 # number of overall misses +system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use +system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67316859 # Number of branches executed +system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate +system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41189464 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value +system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 395375802 # num instructions producing a value +system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle +system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 438834840 72.45% # Type of FU issued + IntMult 6546 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 29 0.00% # Type of FU issued + FloatCmp 5 0.00% # Type of FU issued + FloatCvt 5 0.00% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 124855453 20.61% # Type of FU issued + MemWrite 42021230 6.94% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 5390831 74.54% # attempts to use FU when none available + IntMult 67 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 1490139 20.60% # attempts to use FU when none available + MemWrite 351286 4.86% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 92203773 2772.37% + 1 67051353 2016.09% + 2 80133780 2409.45% + 3 36043478 1083.75% + 4 30084945 904.59% + 5 14579095 438.36% + 6 10850493 326.25% + 7 1143008 34.37% + 8 491187 14.77% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate +system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 66014446 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 66014406 # ITB hits +system.cpu.itb.misses 40 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 181383 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292443 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 85262 # number of replacements +system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use +system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 63236 # number of writebacks +system.cpu.numCycles 334156294 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 4ea4c0572..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:25:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 96bd5579b..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3417919 # Simulator instruction rate (inst/s) -host_mem_usage 193752 # Number of bytes of host memory used -host_seconds 176.09 # Real time elapsed on the host -host_tick_rate 1708971531 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.300931 # Number of seconds simulated -sim_ticks 300930958000 # Number of ticks simulated -system.cpu.dtb.accesses 153970296 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 153965363 # DTB hits -system.cpu.dtb.misses 4933 # DTB misses -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 601861917 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 601861897 # ITB hits -system.cpu.itb.misses 20 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 601861917 # number of cpu cycles simulated -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..4f98f10a9 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:47 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..96bd5579b --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3417919 # Simulator instruction rate (inst/s) +host_mem_usage 193752 # Number of bytes of host memory used +host_seconds 176.09 # Real time elapsed on the host +host_tick_rate 1708971531 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.300931 # Number of seconds simulated +sim_ticks 300930958000 # Number of ticks simulated +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861917 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861897 # ITB hits +system.cpu.itb.misses 20 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index 4f98f10a9..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:47 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 5fbfd3d3d..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1797646 # Simulator instruction rate (inst/s) -host_mem_usage 201208 # Number of bytes of host memory used -host_seconds 334.80 # Real time elapsed on the host -host_tick_rate 2323765799 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.778004 # Number of seconds simulated -sim_ticks 778003833000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses -system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses -system.cpu.dcache.overall_misses 530123 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use -system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325723 # number of writebacks -system.cpu.dtb.accesses 153970296 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 153965363 # DTB hits -system.cpu.dtb.misses 4933 # DTB misses -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use -system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 601861918 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 601861898 # ITB hits -system.cpu.itb.misses 20 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 288954 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84513 # number of replacements -system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63194 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1556007666 # number of cpu cycles simulated -system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..912067c8f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:21:45 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..5fbfd3d3d --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1797646 # Simulator instruction rate (inst/s) +host_mem_usage 201208 # Number of bytes of host memory used +host_seconds 334.80 # Real time elapsed on the host +host_tick_rate 2323765799 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.778004 # Number of seconds simulated +sim_ticks 778003833000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses +system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 153435240 # number of overall hits +system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses +system.cpu.dcache.overall_misses 530123 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use +system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 795 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 601861103 # number of overall hits +system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 795 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use +system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861918 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861898 # ITB hits +system.cpu.itb.misses 20 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 167236 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 288954 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 84513 # number of replacements +system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 63194 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1556007666 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 912067c8f..000000000 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,46 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt deleted file mode 100644 index b1499e0a2..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ /dev/null @@ -1,439 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 182414509 # Number of BTB hits -global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted -global.BPredUnit.lookups 254458067 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116972 # Simulator instruction rate (inst/s) -host_mem_usage 204276 # Number of bytes of host memory used -host_seconds 12016.73 # Real time elapsed on the host -host_tick_rate 91760367 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618365 # Number of instructions simulated -sim_seconds 1.102659 # Number of seconds simulated -sim_ticks 1102659164000 # Number of ticks simulated -system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1964055138 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1088074348 5539.94% - 1 575643775 2930.89% - 2 120435536 613.20% - 3 120975808 615.95% - 4 27955061 142.33% - 5 8084154 41.16% - 6 10447088 53.19% - 7 4343249 22.11% - 8 8096119 41.22% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 1489537508 # Number of instructions committed -system.cpu.commit.COM:loads 402517243 # Number of loads committed -system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375199 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618365 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated -system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency -system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 589980362 # number of overall hits -system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3138202 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 523278 # number of replacements -system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use -system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 348745 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched -system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2203815119 -system.cpu.fetch.rateDist.min_value 0 - 0 1359103013 6167.05% - 1 256500552 1163.89% - 2 81150170 368.23% - 3 38425919 174.36% - 4 85384466 387.44% - 5 41200028 186.95% - 6 32567288 147.78% - 7 20688755 93.88% - 8 288794928 1310.43% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354586500 # number of overall hits -system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2127 # number of overall misses -system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 222 # number of replacements -system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use -system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 128154505 # Number of branches executed -system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate -system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207432555 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value -system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1435567316 # num instructions producing a value -system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle -system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186637130 59.65% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2990817 0.15% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 571681967 28.74% # Type of FU issued - MemWrite 227997762 11.46% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 142220 3.54% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 232758 5.80% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3328923 82.92% # attempts to use FU when none available - MemWrite 310728 7.74% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1083882017 4918.21% - 1 586425796 2660.96% - 2 298714416 1355.44% - 3 164995052 748.68% - 4 47215795 214.25% - 5 14943133 67.81% - 6 6716024 30.47% - 7 790185 3.59% - 8 132701 0.60% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate -system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 214675 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 314078 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84497 # number of replacements -system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61945 # number of writebacks -system.cpu.numCycles 2205318329 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed -system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout new file mode 100755 index 000000000..cf3fc26c2 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:58 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1102659164000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt new file mode 100644 index 000000000..b1499e0a2 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -0,0 +1,439 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 182414509 # Number of BTB hits +global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups +global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted +global.BPredUnit.lookups 254458067 # Number of BP lookups +global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +host_inst_rate 116972 # Simulator instruction rate (inst/s) +host_mem_usage 204276 # Number of bytes of host memory used +host_seconds 12016.73 # Real time elapsed on the host +host_tick_rate 91760367 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1405618365 # Number of instructions simulated +sim_seconds 1.102659 # Number of seconds simulated +sim_ticks 1102659164000 # Number of ticks simulated +system.cpu.commit.COM:branches 86248929 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 1964055138 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 1088074348 5539.94% + 1 575643775 2930.89% + 2 120435536 613.20% + 3 120975808 615.95% + 4 27955061 142.33% + 5 8084154 41.16% + 6 10447088 53.19% + 7 4343249 22.11% + 8 8096119 41.22% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 1489537508 # Number of instructions committed +system.cpu.commit.COM:loads 402517243 # Number of loads committed +system.cpu.commit.COM:membars 51356 # Number of memory barriers committed +system.cpu.commit.COM:refs 569375199 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618365 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated +system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 589980362 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3138202 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 523278 # number of replacements +system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use +system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 348745 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 2203815119 +system.cpu.fetch.rateDist.min_value 0 + 0 1359103013 6167.05% + 1 256500552 1163.89% + 2 81150170 368.23% + 3 38425919 174.36% + 4 85384466 387.44% + 5 41200028 186.95% + 6 32567288 147.78% + 7 20688755 93.88% + 8 288794928 1310.43% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 354586500 # number of overall hits +system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 2127 # number of overall misses +system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 222 # number of replacements +system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use +system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128154505 # Number of branches executed +system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate +system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207432555 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value +system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1435567316 # num instructions producing a value +system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle +system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 1186637130 59.65% # Type of FU issued + IntMult 0 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2990817 0.15% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 571681967 28.74% # Type of FU issued + MemWrite 227997762 11.46% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 142220 3.54% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 232758 5.80% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 3328923 82.92% # attempts to use FU when none available + MemWrite 310728 7.74% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 1083882017 4918.21% + 1 586425796 2660.96% + 2 298714416 1355.44% + 3 164995052 748.68% + 4 47215795 214.25% + 5 14943133 67.81% + 6 6716024 30.47% + 7 790185 3.59% + 8 132701 0.60% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate +system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 214675 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314078 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 84497 # number of replacements +system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.numCycles 2205318329 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed +system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout deleted file mode 100755 index cf3fc26c2..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:58 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1102659164000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 6ee039121..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2833353 # Simulator instruction rate (inst/s) -host_mem_usage 195884 # Number of bytes of host memory used -host_seconds 525.71 # Real time elapsed on the host -host_tick_rate 1416680719 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489523295 # Number of instructions simulated -sim_seconds 0.744764 # Number of seconds simulated -sim_ticks 744764119000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489528239 # number of cpu cycles simulated -system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..959e9811f --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:45:38 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..6ee039121 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2833353 # Simulator instruction rate (inst/s) +host_mem_usage 195884 # Number of bytes of host memory used +host_seconds 525.71 # Real time elapsed on the host +host_tick_rate 1416680719 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 0.744764 # Number of seconds simulated +sim_ticks 744764119000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index 959e9811f..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:45:38 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 21ee70af0..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2121797 # Simulator instruction rate (inst/s) -host_mem_usage 203340 # Number of bytes of host memory used -host_seconds 702.01 # Real time elapsed on the host -host_tick_rate 2963511011 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.080416 # Number of seconds simulated -sim_ticks 2080416155000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568846579 # number of overall hits -system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513081 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316420 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489527099 # number of overall hits -system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1107 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use -system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160847 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293481 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82905 # number of replacements -system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61861 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4160832310 # number of cpu cycles simulated -system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references -system.cpu.workload.PROG:num_syscalls 49 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..ee69ae99e --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..696328daa --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:41:13 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2080416155000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..21ee70af0 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2121797 # Simulator instruction rate (inst/s) +host_mem_usage 203340 # Number of bytes of host memory used +host_seconds 702.01 # Real time elapsed on the host +host_tick_rate 2963511011 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.080416 # Number of seconds simulated +sim_ticks 2080416155000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses +system.cpu.dcache.overall_misses 513081 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316420 # number of writebacks +system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 1107 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use +system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 160847 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293481 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 82905 # number of replacements +system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61861 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4160832310 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index ee69ae99e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 696328daa..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:41:13 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2080416155000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 4f9664bbc..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1613706 # Simulator instruction rate (inst/s) -host_mem_usage 195008 # Number of bytes of host memory used -host_seconds 1003.53 # Real time elapsed on the host -host_tick_rate 959566027 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 0.962952 # Number of seconds simulated -sim_ticks 962951801000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925903603 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..12f446c64 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..7b8dadcc0 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 23:03:02 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 23:03:28 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 962951801000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..4f9664bbc --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1613706 # Simulator instruction rate (inst/s) +host_mem_usage 195008 # Number of bytes of host memory used +host_seconds 1003.53 # Real time elapsed on the host +host_tick_rate 959566027 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 0.962952 # Number of seconds simulated +sim_ticks 962951801000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1925903603 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr deleted file mode 100755 index 12f446c64..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr +++ /dev/null @@ -1,9 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout deleted file mode 100755 index 7b8dadcc0..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:03:28 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 962951801000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt deleted file mode 100644 index 76b073830..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,234 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1159099 # Simulator instruction rate (inst/s) -host_mem_usage 201888 # Number of bytes of host memory used -host_seconds 1397.12 # Real time elapsed on the host -host_tick_rate 1828142910 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 2.554133 # Number of seconds simulated -sim_ticks 2554132875000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses -system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606644555 # number of overall hits -system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses -system.cpu.dcache.overall_misses 506099 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 439707 # number of replacements -system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use -system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 721 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925902841 # number of overall hits -system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 721 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use -system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 161820 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 282704 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82097 # number of replacements -system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use -system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61702 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108265750 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..12f446c64 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: instruction 'prefetch_t0' unimplemented +warn: Increasing stack size by one page. +warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..5b0e0d9ff --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 7 2008 03:21:37 +M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 +M5 commit date Thu Nov 06 23:13:50 2008 -0800 +M5 started Nov 8 2008 00:23:58 +M5 executing on tater +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2554132875000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..76b073830 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1159099 # Simulator instruction rate (inst/s) +host_mem_usage 201888 # Number of bytes of host memory used +host_seconds 1397.12 # Real time elapsed on the host +host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1619398860 # Number of instructions simulated +sim_seconds 2.554133 # Number of seconds simulated +sim_ticks 2554132875000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses +system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses +system.cpu.dcache.overall_misses 506099 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 439707 # number of replacements +system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use +system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 308507 # number of writebacks +system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 721 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 721 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use +system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 161820 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 282704 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 82097 # number of replacements +system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61702 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5108265750 # number of cpu cycles simulated +system.cpu.num_insts 1619398860 # Number of instructions executed +system.cpu.num_refs 607161871 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr b/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr deleted file mode 100755 index 12f446c64..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stderr +++ /dev/null @@ -1,9 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented -warn: instruction 'fldcw_Mw' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: instruction 'prefetch_t0' unimplemented -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout b/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout deleted file mode 100755 index 5b0e0d9ff..000000000 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stdout +++ /dev/null @@ -1,47 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:23:58 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Duplicating 262144 bytes -Duplicating 524288 bytes -Input data 1048576 bytes in length -Compressing Input Data, level 1 -Compressed data 108074 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 3 -Compressed data 97831 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 5 -Compressed data 83382 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 7 -Compressed data 76606 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 73189 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2554132875000 because target called exit() -- cgit v1.2.3