From d824af340ec98a9d7ac34a3c358666191df1f83f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Feb 2009 17:02:16 -0800 Subject: X86: Update stats now that the micropc isn't always reset on faults. --- .../00.gzip/ref/x86/linux/simple-atomic/config.ini | 2 +- .../00.gzip/ref/x86/linux/simple-atomic/simout | 14 ++--- .../00.gzip/ref/x86/linux/simple-atomic/stats.txt | 20 ++++---- .../00.gzip/ref/x86/linux/simple-timing/config.ini | 2 +- .../00.gzip/ref/x86/linux/simple-timing/simout | 14 ++--- .../00.gzip/ref/x86/linux/simple-timing/stats.txt | 60 +++++++++++----------- 6 files changed, 56 insertions(+), 56 deletions(-) (limited to 'tests/long/00.gzip/ref') diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index fb96ff412..93e326b16 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 7b8dadcc0..81b1be1e0 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:03:28 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:19:42 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 962951801000 because target called exit() +Exiting @ tick 962935342000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 4f9664bbc..fcdb37b5a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1613706 # Simulator instruction rate (inst/s) -host_mem_usage 195008 # Number of bytes of host memory used -host_seconds 1003.53 # Real time elapsed on the host -host_tick_rate 959566027 # Simulator tick rate (ticks/s) +host_inst_rate 717061 # Simulator instruction rate (inst/s) +host_mem_usage 197184 # Number of bytes of host memory used +host_seconds 2258.34 # Real time elapsed on the host +host_tick_rate 426391006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 0.962952 # Number of seconds simulated -sim_ticks 962951801000 # Number of ticks simulated +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 0.962935 # Number of seconds simulated +sim_ticks 962935342000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925903603 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 1925870685 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 7d5cc5629..4630d922d 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 5b0e0d9ff..7f0c2942c 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:23:58 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:22:06 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554132875000 because target called exit() +Exiting @ tick 2554098117000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 76b073830..89a1a5647 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159099 # Simulator instruction rate (inst/s) -host_mem_usage 201888 # Number of bytes of host memory used -host_seconds 1397.12 # Real time elapsed on the host -host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +host_inst_rate 511923 # Simulator instruction rate (inst/s) +host_mem_usage 204640 # Number of bytes of host memory used +host_seconds 3163.30 # Real time elapsed on the host +host_tick_rate 807415286 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 2.554133 # Number of seconds simulated -sim_ticks 2554132875000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 2.554098 # Number of seconds simulated +sim_ticks 2554098117000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # m system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 506099 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_hits 606642715 # number of overall hits system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses system.cpu.dcache.overall_misses 506099 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use -system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.609383 # Cycle average of tags in use +system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1593417000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1925870644 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1925869923 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2671109.463245 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1925870644 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1925869923 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 721 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1925870644 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_hits 1925869923 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use -system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 658.724449 # Cycle average of tags in use +system.cpu.icache.total_refs 1925869923 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16428.000401 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108265750 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 5108196234 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3