From 3204f968091d32846a59c0666157c6c8946842d1 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 16 Feb 2008 14:58:37 -0500 Subject: Update stats for new writeback behavior. --HG-- extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14 --- .../ref/sparc/linux/simple-timing/m5stats.txt | 103 ++++++++++----------- .../10.mcf/ref/sparc/linux/simple-timing/stdout | 8 +- 2 files changed, 54 insertions(+), 57 deletions(-) (limited to 'tests/long/10.mcf/ref/sparc') diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 433654cb0..f11af3267 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2004505 # Simulator instruction rate (inst/s) -host_mem_usage 316136 # Number of bytes of host memory used -host_seconds 121.64 # Real time elapsed on the host -host_tick_rate 2987214089 # Simulator tick rate (ticks/s) +host_inst_rate 588725 # Simulator instruction rate (inst/s) +host_mem_usage 293504 # Number of bytes of host memory used +host_seconds 414.17 # Real time elapsed on the host +host_tick_rate 875417785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.363367 # Number of seconds simulated -sim_ticks 363367019000 # Number of ticks simulated +sim_seconds 0.362567 # Number of seconds simulated +sim_ticks 362567483000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13898.235302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11898.235302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13002.741800 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.741800 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12408956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 11609420000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10623268000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 9823732000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14965.505407 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14156.100331 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14783031000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 13983495000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12807417000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 12007881000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14965.505407 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14156.100331 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 104133498 # number of overall hits -system.cpu.dcache.overall_miss_latency 14783031000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 13983495000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses system.cpu.dcache.overall_misses 987807 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12807417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 12007881000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,9 +86,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 935465 # number of replacements system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3566.815369 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3565.653949 # Cycle average of tags in use system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134193669000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134187537000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency @@ -148,7 +148,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.847005 # Cycle average of tags in use +system.cpu.icache.tagsinuse 716.707891 # Cycle average of tags in use system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -165,13 +165,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 46717 # nu system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 826014 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1489598000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.075761 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 67709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 744799000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075761 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 67709 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 892642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23782000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11891000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -182,13 +182,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 94875 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 94875 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 48.787024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 51.564846 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -197,14 +194,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 826014 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2517372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.121673 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 114426 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 892642 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1051556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050825 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47798 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1258686000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.121673 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 114426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 525778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47798 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -212,14 +209,14 @@ system.cpu.l2cache.overall_accesses 940440 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 826014 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2517372000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.121673 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 114426 # number of overall misses +system.cpu.l2cache.overall_hits 892642 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1051556000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050825 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47798 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1258686000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.121673 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 114426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 525778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050825 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47798 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +228,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 829 # number of replacements -system.cpu.l2cache.sampled_refs 11344 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 877 # number of replacements +system.cpu.l2cache.sampled_refs 15560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8106.277957 # Cycle average of tags in use -system.cpu.l2cache.total_refs 553440 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8927.933046 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802349 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 726734038 # number of cpu cycles simulated +system.cpu.numCycles 725134966 # number of cpu cycles simulated system.cpu.num_insts 243829010 # Number of instructions executed system.cpu.num_refs 105710359 # Number of memory references system.cpu.workload.PROG:num_syscalls 428 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 9e3602fb0..1766c5984 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -21,9 +21,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 18:26:14 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 363367019000 because target called exit() +Exiting @ tick 362567483000 because target called exit() -- cgit v1.2.3