From 9e45ada1718b6df9310757fdc7cd78db4695516f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 9 Sep 2010 14:40:19 -0400 Subject: stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. --- .../30.eon/ref/arm/linux/simple-timing/config.ini | 2 +- .../long/30.eon/ref/arm/linux/simple-timing/simout | 12 +- .../30.eon/ref/arm/linux/simple-timing/stats.txt | 147 +++++++++++---------- 3 files changed, 82 insertions(+), 79 deletions(-) (limited to 'tests/long/30.eon/ref/arm/linux') diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 09f490b9e..9a41cf5e7 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index d8c065b6e..13d544b5b 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:37:41 +M5 compiled Aug 26 2010 13:52:30 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:52:33 M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -18,4 +20,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.520000 -Exiting @ tick 525836291000 because target called exit() +Exiting @ tick 525827779000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index ccb6f986c..ac525a38a 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1023413 # Simulator instruction rate (inst/s) -host_mem_usage 218276 # Number of bytes of host memory used -host_seconds 336.52 # Real time elapsed on the host -host_tick_rate 1562566741 # Simulator tick rate (ticks/s) +host_inst_rate 898977 # Simulator instruction rate (inst/s) +host_mem_usage 219380 # Number of bytes of host memory used +host_seconds 383.10 # Real time elapsed on the host +host_tick_rate 1372552338 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 344399678 # Number of instructions simulated -sim_seconds 0.525836 # Number of seconds simulated -sim_ticks 525836291000 # Number of ticks simulated +sim_seconds 0.525828 # Number of seconds simulated +sim_ticks 525827779000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 82060523 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 170744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000037 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3049 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 161597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000037 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3049 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 82060677 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 162078000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2895 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 153393000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2895 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 53835.051546 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency -system.cpu.dcache.demand_hits 176645641 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 250656000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4656 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 53751.665926 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency +system.cpu.dcache.demand_hits 176645795 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 241990000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4502 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 236688000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4656 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 228484000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4502 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.751811 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3079.417400 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3079.430321 # Average occupied blocks per context system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 53835.051546 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 53751.665926 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 176645641 # number of overall hits -system.cpu.dcache.overall_miss_latency 250656000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4656 # number of overall misses +system.cpu.dcache.overall_hits 176645795 # number of overall hits +system.cpu.dcache.overall_miss_latency 241990000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4502 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 236688000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4656 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 228484000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4502 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1332 # number of replacements system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3079.417400 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3079.430321 # Cycle average of tags in use system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 974 # number of writebacks @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 15603 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.862302 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1765.994016 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1766.000778 # Average occupied blocks per context system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13796 # number of replacements system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.994016 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1766.000778 # Cycle average of tags in use system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 149344000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 2872 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 114880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 2872 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 149292000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.999652 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 2871 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 114840000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999652 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 2871 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -166,20 +167,20 @@ system.cpu.l2cache.ReadReq_misses 3977 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 177 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 9204000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1196000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 177 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7080000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 920000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 177 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.776587 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.717391 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 13233 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 356148000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.341052 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 6849 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 13234 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 356096000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.341002 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 6848 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 273960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.341052 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 6849 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 273920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.341002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 6848 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.091337 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.010370 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2992.938866 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 339.814124 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.010365 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3134.105136 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 339.639233 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 13233 # number of overall hits -system.cpu.l2cache.overall_miss_latency 356148000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.341052 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 6849 # number of overall misses +system.cpu.l2cache.overall_hits 13234 # number of overall hits +system.cpu.l2cache.overall_miss_latency 356096000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.341002 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 6848 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 273960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.341052 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 6849 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 273920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.341002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 6848 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 48 # number of replacements -system.cpu.l2cache.sampled_refs 4758 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4876 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3332.752990 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3473.744369 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13250 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1051672582 # number of cpu cycles simulated +system.cpu.numCycles 1051655558 # number of cpu cycles simulated system.cpu.num_insts 344399678 # Number of instructions executed system.cpu.num_refs 177028576 # Number of memory references system.cpu.workload.PROG:num_syscalls 191 # Number of system calls -- cgit v1.2.3