From f7885b8f260ca11c2f4a405525d9fc4e554f41a8 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 18 Jan 2011 16:30:06 -0600 Subject: ARM/O3: Add regressions for ARM w/ O3 CPU. --- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100755 tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr (limited to 'tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr') diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr new file mode 100755 index 000000000..75c1cafaa --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr @@ -0,0 +1,7 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: fcntl64(3, 2) passed through to host +For more information see: http://www.m5sim.org/warn/a55e2c46 +warn: Bad interworking branch address 0x66. +For more information see: http://www.m5sim.org/warn/55f199fd +hack: be nice to actually delete the event here -- cgit v1.2.3