From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 25 Jan 2012 17:19:50 +0000 Subject: stats: Update stats for final tick and memory bandwidth patches --- .../ref/alpha/tru64/inorder-timing/config.ini | 10 ++++++---- .../50.vortex/ref/alpha/tru64/inorder-timing/simout | 6 +++--- .../ref/alpha/tru64/inorder-timing/stats.txt | 19 +++++++++++++++---- .../50.vortex/ref/alpha/tru64/o3-timing/config.ini | 8 +++++--- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 6 ++---- .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 19 +++++++++++++++---- .../ref/alpha/tru64/simple-atomic/config.ini | 13 ++++++++----- .../50.vortex/ref/alpha/tru64/simple-atomic/simout | 8 ++++---- .../50.vortex/ref/alpha/tru64/simple-atomic/stats.txt | 19 +++++++++++++++---- .../ref/alpha/tru64/simple-timing/config.ini | 11 +++++++---- .../50.vortex/ref/alpha/tru64/simple-timing/simout | 8 ++++---- .../50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 19 +++++++++++++++---- 12 files changed, 99 insertions(+), 47 deletions(-) (limited to 'tests/long/50.vortex/ref/alpha/tru64') diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index e20a60e8c..1b963b10c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=InOrderCPU @@ -182,7 +184,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -205,7 +207,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -224,7 +226,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -234,5 +236,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index a3cf9c876..0aab67a06 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 16:45:59 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:28:56 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index a84fb4906..32a07ce20 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.046914 # Number of seconds simulated sim_ticks 46914279500 # Number of ticks simulated +final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53929 # Simulator instruction rate (inst/s) -host_tick_rate 28639497 # Simulator tick rate (ticks/s) -host_mem_usage 254456 # Number of bytes of host memory used -host_seconds 1638.10 # Real time elapsed on the host +host_inst_rate 107347 # Simulator instruction rate (inst/s) +host_tick_rate 57007816 # Simulator tick rate (ticks/s) +host_mem_usage 216192 # Number of bytes of host memory used +host_seconds 822.94 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +system.physmem.bytes_read 11164096 # Number of bytes read from this memory +system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7712960 # Number of bytes written to this memory +system.physmem.num_reads 174439 # Number of read requests responded to by this memory +system.physmem.num_writes 120515 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 2f92d3206..ea038d4da 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 6c1f5182e..9e435cc97 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 16:10:02 -gem5 started Aug 20 2011 16:10:08 +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:35:02 gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index a5baa0129..9c4b77b7d 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.021260 # Number of seconds simulated sim_ticks 21259532000 # Number of ticks simulated +final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184165 # Simulator instruction rate (inst/s) -host_tick_rate 49191900 # Simulator tick rate (ticks/s) -host_mem_usage 214460 # Number of bytes of host memory used -host_seconds 432.18 # Real time elapsed on the host +host_inst_rate 187781 # Simulator instruction rate (inst/s) +host_tick_rate 50157547 # Simulator tick rate (ticks/s) +host_mem_usage 217440 # Number of bytes of host memory used +host_seconds 423.86 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated +system.physmem.bytes_read 11229312 # Number of bytes read from this memory +system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713344 # Number of bytes written to this memory +system.physmem.num_reads 175458 # Number of read requests responded to by this memory +system.physmem.num_writes 120521 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index d98970549..d8535707b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaTLB @@ -61,7 +64,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index c4b225cf1..160c80ddb 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 12:18:39 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:42:17 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 1ca39fde6..4fc91e266 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.044221 # Number of seconds simulated sim_ticks 44221003000 # Number of ticks simulated +final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3266324 # Simulator instruction rate (inst/s) -host_tick_rate 1635033806 # Simulator tick rate (ticks/s) -host_mem_usage 192576 # Number of bytes of host memory used -host_seconds 27.05 # Real time elapsed on the host +host_inst_rate 3998504 # Simulator instruction rate (inst/s) +host_tick_rate 2001543652 # Simulator tick rate (ticks/s) +host_mem_usage 206876 # Number of bytes of host memory used +host_seconds 22.09 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +system.physmem.bytes_read 480454939 # Number of bytes read from this memory +system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_written 91652896 # Number of bytes written to this memory +system.physmem.num_reads 108714711 # Number of read requests responded to by this memory +system.physmem.num_writes 14613377 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 10864858470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 12937468537 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 7e8e19e97..f99b5fb55 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -146,7 +149,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -164,7 +167,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -188,7 +191,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -198,5 +201,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index eff2b3a97..e74b48d2a 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 20 2011 12:44:27 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:42:49 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 02c53f6a1..59b869a9f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -2,12 +2,23 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.134277 # Number of seconds simulated sim_ticks 134276988000 # Number of ticks simulated +final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1277823 # Simulator instruction rate (inst/s) -host_tick_rate 1942278600 # Simulator tick rate (ticks/s) -host_mem_usage 201212 # Number of bytes of host memory used -host_seconds 69.13 # Real time elapsed on the host +host_inst_rate 1801981 # Simulator instruction rate (inst/s) +host_tick_rate 2738992827 # Simulator tick rate (ticks/s) +host_mem_usage 215584 # Number of bytes of host memory used +host_seconds 49.02 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +system.physmem.bytes_read 11121920 # Number of bytes read from this memory +system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7712384 # Number of bytes written to this memory +system.physmem.num_reads 173780 # Number of read requests responded to by this memory +system.physmem.num_writes 120506 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv -- cgit v1.2.3