From 19273164da50011d59b7f362026f8e80260807d4 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 8 Dec 2008 07:16:40 -0800 Subject: output: Change default output directory and files and update tests. --HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt --- .../ref/alpha/tru64/o3-timing/m5stats.txt | 449 ---------------- .../50.vortex/ref/alpha/tru64/o3-timing/simerr | 2 + .../50.vortex/ref/alpha/tru64/o3-timing/simout | 15 + .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 449 ++++++++++++++++ .../50.vortex/ref/alpha/tru64/o3-timing/stderr | 2 - .../50.vortex/ref/alpha/tru64/o3-timing/stdout | 15 - .../ref/alpha/tru64/simple-atomic/m5stats.txt | 34 -- .../50.vortex/ref/alpha/tru64/simple-atomic/simerr | 2 + .../50.vortex/ref/alpha/tru64/simple-atomic/simout | 15 + .../ref/alpha/tru64/simple-atomic/stats.txt | 34 ++ .../50.vortex/ref/alpha/tru64/simple-atomic/stderr | 2 - .../50.vortex/ref/alpha/tru64/simple-atomic/stdout | 15 - .../ref/alpha/tru64/simple-timing/m5stats.txt | 250 --------- .../50.vortex/ref/alpha/tru64/simple-timing/simerr | 2 + .../50.vortex/ref/alpha/tru64/simple-timing/simout | 15 + .../ref/alpha/tru64/simple-timing/stats.txt | 250 +++++++++ .../50.vortex/ref/alpha/tru64/simple-timing/stderr | 2 - .../50.vortex/ref/alpha/tru64/simple-timing/stdout | 15 - .../ref/sparc/linux/simple-atomic/m5stats.txt | 18 - .../50.vortex/ref/sparc/linux/simple-atomic/simerr | 564 +++++++++++++++++++++ .../50.vortex/ref/sparc/linux/simple-atomic/simout | 16 + .../ref/sparc/linux/simple-atomic/stats.txt | 18 + .../50.vortex/ref/sparc/linux/simple-atomic/stderr | 564 --------------------- .../50.vortex/ref/sparc/linux/simple-atomic/stdout | 16 - .../ref/sparc/linux/simple-timing/m5stats.txt | 244 --------- .../50.vortex/ref/sparc/linux/simple-timing/simerr | 564 +++++++++++++++++++++ .../50.vortex/ref/sparc/linux/simple-timing/simout | 16 + .../ref/sparc/linux/simple-timing/stats.txt | 244 +++++++++ .../50.vortex/ref/sparc/linux/simple-timing/stderr | 564 --------------------- .../50.vortex/ref/sparc/linux/simple-timing/stdout | 16 - 30 files changed, 2206 insertions(+), 2206 deletions(-) delete mode 100644 tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt create mode 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr create mode 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout create mode 100644 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout delete mode 100644 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt create mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr create mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout create mode 100644 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout delete mode 100644 tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt create mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr create mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout create mode 100644 tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr delete mode 100755 tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout delete mode 100644 tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt create mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr create mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout create mode 100644 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt delete mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr delete mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout delete mode 100644 tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt create mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr create mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-timing/simout create mode 100644 tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt delete mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr delete mode 100755 tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout (limited to 'tests/long/50.vortex/ref') diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt deleted file mode 100644 index 36c3049e3..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ /dev/null @@ -1,449 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8039250 # Number of BTB hits -global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted -global.BPredUnit.lookups 16249463 # Number of BP lookups -global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. -host_inst_rate 155507 # Simulator instruction rate (inst/s) -host_mem_usage 212996 # Number of bytes of host memory used -host_seconds 511.82 # Real time elapsed on the host -host_tick_rate 53016132 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134794500 # Number of ticks simulated -system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51751168 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22506445 4348.97% - 1 11357579 2194.65% - 2 5114502 988.29% - 3 3560855 688.07% - 4 2552504 493.23% - 5 1532717 296.17% - 6 1008933 194.96% - 7 796739 153.96% - 8 3320894 641.70% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 88340672 # Number of instructions committed -system.cpu.commit.COM:loads 20379399 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 35224018 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit -system.cpu.committedInsts 79591756 # Number of Instructions Simulated -system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838925 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199965 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200933 # number of replacements -system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36599689 # DTB accesses -system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36425481 # DTB hits -system.cpu.dtb.misses 174208 # DTB misses -system.cpu.dtb.read_accesses 21541288 # DTB read accesses -system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383020 # DTB read hits -system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058401 # DTB write accesses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042461 # DTB write hits -system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53041270 -system.cpu.fetch.rateDist.min_value 0 - 0 33206277 6260.46% - 1 1871594 352.86% - 2 1529415 288.34% - 3 1809626 341.17% - 4 3985239 751.35% - 5 1867239 352.04% - 6 695846 131.19% - 7 1111736 209.60% - 8 6964298 1313.00% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297366 # number of overall hits -system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88706 # number of overall misses -system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83888 # number of replacements -system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use -system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745486 # Number of branches executed -system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate -system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291392 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value -system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396987 # num instructions producing a value -system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 47898565 56.12% # Type of FU issued - IntMult 42953 0.05% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 121655 0.14% # Type of FU issued - FloatCmp 88 0.00% # Type of FU issued - FloatCvt 122104 0.14% # Type of FU issued - FloatMult 53 0.00% # Type of FU issued - FloatDiv 38535 0.05% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 21753622 25.49% # Type of FU issued - MemWrite 15368770 18.01% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 97100 9.91% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 470602 48.04% # attempts to use FU when none available - MemWrite 411938 42.05% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17563410 3311.27% - 1 13937999 2627.76% - 2 8266125 1558.43% - 3 4784809 902.09% - 4 4627568 872.45% - 5 2066740 389.65% - 6 1112374 209.72% - 7 454507 85.69% - 8 227738 42.94% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13412237 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13386072 # ITB hits -system.cpu.itb.misses 26165 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102894 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188071 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 148779 # number of replacements -system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use -system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.numCycles 54269590 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed -system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..305b9e178 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:27:20 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt new file mode 100644 index 000000000..36c3049e3 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,449 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 8039250 # Number of BTB hits +global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted +global.BPredUnit.lookups 16249463 # Number of BP lookups +global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +host_inst_rate 155507 # Simulator instruction rate (inst/s) +host_mem_usage 212996 # Number of bytes of host memory used +host_seconds 511.82 # Real time elapsed on the host +host_tick_rate 53016132 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 79591756 # Number of instructions simulated +sim_seconds 0.027135 # Number of seconds simulated +sim_ticks 27134794500 # Number of ticks simulated +system.cpu.commit.COM:branches 13754477 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 51751168 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 22506445 4348.97% + 1 11357579 2194.65% + 2 5114502 988.29% + 3 3560855 688.07% + 4 2552504 493.23% + 5 1532717 296.17% + 6 1008933 194.96% + 7 796739 153.96% + 8 3320894 641.70% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 88340672 # Number of instructions committed +system.cpu.commit.COM:loads 20379399 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 35224018 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit +system.cpu.committedInsts 79591756 # Number of Instructions Simulated +system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated +system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 33838925 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1199965 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 200933 # number of replacements +system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147760 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599689 # DTB accesses +system.cpu.dtb.acv 39 # DTB access violations +system.cpu.dtb.hits 36425481 # DTB hits +system.cpu.dtb.misses 174208 # DTB misses +system.cpu.dtb.read_accesses 21541288 # DTB read accesses +system.cpu.dtb.read_acv 37 # DTB read access violations +system.cpu.dtb.read_hits 21383020 # DTB read hits +system.cpu.dtb.read_misses 158268 # DTB read misses +system.cpu.dtb.write_accesses 15058401 # DTB write accesses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_hits 15042461 # DTB write hits +system.cpu.dtb.write_misses 15940 # DTB write misses +system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched +system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 53041270 +system.cpu.fetch.rateDist.min_value 0 + 0 33206277 6260.46% + 1 1871594 352.86% + 2 1529415 288.34% + 3 1809626 341.17% + 4 3985239 751.35% + 5 1867239 352.04% + 6 695846 131.19% + 7 1111736 209.60% + 8 6964298 1313.00% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses +system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 13297366 # number of overall hits +system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses +system.cpu.icache.overall_misses 88706 # number of overall misses +system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 83888 # number of replacements +system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use +system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745486 # Number of branches executed +system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate +system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291392 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value +system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 32396987 # num instructions producing a value +system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle +system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + No_OpClass 0 0.00% # Type of FU issued + IntAlu 47898565 56.12% # Type of FU issued + IntMult 42953 0.05% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 121655 0.14% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122104 0.14% # Type of FU issued + FloatMult 53 0.00% # Type of FU issued + FloatDiv 38535 0.05% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 21753622 25.49% # Type of FU issued + MemWrite 15368770 18.01% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 97100 9.91% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 470602 48.04% # attempts to use FU when none available + MemWrite 411938 42.05% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 17563410 3311.27% + 1 13937999 2627.76% + 2 8266125 1558.43% + 3 4784809 902.09% + 4 4627568 872.45% + 5 2066740 389.65% + 6 1112374 209.72% + 7 454507 85.69% + 8 227738 42.94% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate +system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13412237 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 13386072 # ITB hits +system.cpu.itb.misses 26165 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 102894 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188071 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 148779 # number of replacements +system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.numCycles 54269590 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed +system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout deleted file mode 100755 index 305b9e178..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:27:20 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt deleted file mode 100644 index 7b2d6e4f7..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ /dev/null @@ -1,34 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3156054 # Simulator instruction rate (inst/s) -host_mem_usage 203904 # Number of bytes of host memory used -host_seconds 27.99 # Real time elapsed on the host -host_tick_rate 1579824710 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -system.cpu.dtb.accesses 34987415 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 34890015 # DTB hits -system.cpu.dtb.misses 97400 # DTB misses -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 88442007 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 88438073 # ITB hits -system.cpu.itb.misses 3934 # ITB misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..f78544a3c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:24:43 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt new file mode 100644 index 000000000..7b2d6e4f7 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3156054 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 27.99 # Real time elapsed on the host +host_tick_rate 1579824710 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.044221 # Number of seconds simulated +sim_ticks 44221003000 # Number of ticks simulated +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442007 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438073 # ITB hits +system.cpu.itb.misses 3934 # ITB misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100755 index f78544a3c..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:24:43 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt deleted file mode 100644 index 4078e993e..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ /dev/null @@ -1,250 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1655989 # Simulator instruction rate (inst/s) -host_mem_usage 211348 # Number of bytes of host memory used -host_seconds 53.35 # Real time elapsed on the host -host_tick_rate 2533794438 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.135169 # Number of seconds simulated -sim_ticks 135168766000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses -system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34679456 # number of overall hits -system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses -system.cpu.dcache.overall_misses 210559 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147714 # number of writebacks -system.cpu.dtb.accesses 34987415 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 34890015 # DTB hits -system.cpu.dtb.misses 97400 # DTB misses -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency -system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_misses 76436 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use -system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 88442008 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 88438074 # ITB hits -system.cpu.itb.misses 3934 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186875 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 147561 # number of replacements -system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use -system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120634 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270337532 # number of cpu cycles simulated -system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr new file mode 100755 index 000000000..cd7a7fb23 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..7c7d8426c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,15 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Dec 4 2008 21:21:43 +M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 +M5 commit date Thu Dec 04 18:04:32 2008 -0500 +M5 started Dec 4 2008 21:28:00 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..4078e993e --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1655989 # Simulator instruction rate (inst/s) +host_mem_usage 211348 # Number of bytes of host memory used +host_seconds 53.35 # Real time elapsed on the host +host_tick_rate 2533794438 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168766000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses +system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 34679456 # number of overall hits +system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses +system.cpu.dcache.overall_misses 210559 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 200248 # number of replacements +system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147714 # number of writebacks +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency +system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses +system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 88361638 # number of overall hits +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses +system.cpu.icache.overall_misses 76436 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 74391 # number of replacements +system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use +system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442008 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438074 # ITB hits +system.cpu.itb.misses 3934 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 93905 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186875 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 147561 # number of replacements +system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use +system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 120634 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 270337532 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr deleted file mode 100755 index cd7a7fb23..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout deleted file mode 100755 index 7c7d8426c..000000000 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,15 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:28:00 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt deleted file mode 100644 index 25cbdfb32..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ /dev/null @@ -1,18 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 2431097 # Simulator instruction rate (inst/s) -host_mem_usage 204768 # Number of bytes of host memory used -host_seconds 56.00 # Real time elapsed on the host -host_tick_rate 1216955986 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148678500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 136297358 # number of cpu cycles simulated -system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..06afeeef2 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,564 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026527848, 4026528248, ...) +warn: ignoring syscall time(4026527400, 1375098, ...) +warn: ignoring syscall time(4026527312, 1, ...) +warn: ignoring syscall time(4026527048, 413, ...) +warn: ignoring syscall time(4026527048, 414, ...) +warn: ignoring syscall time(4026527288, 4026527688, ...) +warn: ignoring syscall time(4026526840, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526960, 409, ...) +warn: ignoring syscall time(4026527040, 409, ...) +warn: ignoring syscall time(4026527000, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526312, 19045, ...) +warn: ignoring syscall time(4026526832, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526936, 409, ...) +warn: ignoring syscall time(4026527008, 4026527408, ...) +warn: ignoring syscall time(4026526560, 1375098, ...) +warn: ignoring syscall time(4026527184, 18732, ...) +warn: ignoring syscall time(4026526632, 409, ...) +warn: ignoring syscall time(4026526736, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527744, 225, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026527096, 4026527496, ...) +warn: ignoring syscall time(4026526648, 1375098, ...) +warn: ignoring syscall time(4026526824, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527184, 1879089152, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall time(4026527472, 1595768, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026525968, 20500, ...) +warn: ignoring syscall time(4026525968, 4026526436, ...) +warn: ignoring syscall time(4026526056, 7004192, ...) +warn: ignoring syscall time(4026527512, 4, ...) +warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout new file mode 100755 index 000000000..b0eadd5ad --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:55:47 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..25cbdfb32 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2431097 # Simulator instruction rate (inst/s) +host_mem_usage 204768 # Number of bytes of host memory used +host_seconds 56.00 # Real time elapsed on the host +host_tick_rate 1216955986 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136139203 # Number of instructions simulated +sim_seconds 0.068149 # Number of seconds simulated +sim_ticks 68148678500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 136297358 # number of cpu cycles simulated +system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr deleted file mode 100755 index 06afeeef2..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,564 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout deleted file mode 100755 index b0eadd5ad..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:55:47 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 68148678500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt deleted file mode 100644 index 9b35ba579..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ /dev/null @@ -1,244 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1344201 # Simulator instruction rate (inst/s) -host_mem_usage 212228 # Number of bytes of host memory used -host_seconds 101.28 # Real time elapsed on the host -host_tick_rate 2025263348 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.205117 # Number of seconds simulated -sim_ticks 205116920000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency -system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses -system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses -system.cpu.dcache.overall_misses 154904 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107271 # number of writebacks -system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses -system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses -system.cpu.icache.overall_misses 187024 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use -system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 144925 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 120486 # number of replacements -system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use -system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 87413 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 410233840 # number of cpu cycles simulated -system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..06afeeef2 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,564 @@ +warn: Sockets disabled, not accepting gdb connections +warn: ignoring syscall time(4026527848, 4026528248, ...) +warn: ignoring syscall time(4026527400, 1375098, ...) +warn: ignoring syscall time(4026527312, 1, ...) +warn: ignoring syscall time(4026527048, 413, ...) +warn: ignoring syscall time(4026527048, 414, ...) +warn: ignoring syscall time(4026527288, 4026527688, ...) +warn: ignoring syscall time(4026526840, 1375098, ...) +warn: Increasing stack size by one page. +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526960, 409, ...) +warn: ignoring syscall time(4026527040, 409, ...) +warn: ignoring syscall time(4026527000, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526984, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526312, 19045, ...) +warn: ignoring syscall time(4026526832, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526840, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526848, 409, ...) +warn: ignoring syscall time(4026526936, 409, ...) +warn: ignoring syscall time(4026527008, 4026527408, ...) +warn: ignoring syscall time(4026526560, 1375098, ...) +warn: ignoring syscall time(4026527184, 18732, ...) +warn: ignoring syscall time(4026526632, 409, ...) +warn: ignoring syscall time(4026526736, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527744, 225, ...) +warn: ignoring syscall time(4026527048, 409, ...) +warn: ignoring syscall time(4026526856, 409, ...) +warn: ignoring syscall time(4026526872, 409, ...) +warn: ignoring syscall time(4026527096, 4026527496, ...) +warn: ignoring syscall time(4026526648, 1375098, ...) +warn: ignoring syscall time(4026526824, 0, ...) +warn: ignoring syscall time(4026527320, 0, ...) +warn: ignoring syscall time(4026527184, 1879089152, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall times(4026527728, 246, ...) +warn: ignoring syscall time(4026527472, 1595768, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026527472, 0, ...) +warn: ignoring syscall time(4026526912, 19045, ...) +warn: ignoring syscall time(4026526912, 17300, ...) +warn: ignoring syscall time(4026525968, 20500, ...) +warn: ignoring syscall time(4026525968, 4026526436, ...) +warn: ignoring syscall time(4026526056, 7004192, ...) +warn: ignoring syscall time(4026527512, 4, ...) +warn: ignoring syscall time(4026525760, 0, ...) +warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..2b1927ccc --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 22:40:47 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:43:57 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 205116920000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..9b35ba579 --- /dev/null +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1344201 # Simulator instruction rate (inst/s) +host_mem_usage 212228 # Number of bytes of host memory used +host_seconds 101.28 # Real time elapsed on the host +host_tick_rate 2025263348 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 136139203 # Number of instructions simulated +sim_seconds 0.205117 # Number of seconds simulated +sim_ticks 205116920000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses +system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 57940701 # number of overall hits +system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses +system.cpu.dcache.overall_misses 154904 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 146582 # number of replacements +system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use +system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107271 # number of writebacks +system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency +system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses +system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 136106788 # number of overall hits +system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses +system.cpu.icache.overall_misses 187024 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 184976 # number of replacements +system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use +system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 192777 # number of overall hits +system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 144925 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 120486 # number of replacements +system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use +system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 87413 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 410233840 # number of cpu cycles simulated +system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr deleted file mode 100755 index 06afeeef2..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,564 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026527848, 4026528248, ...) -warn: ignoring syscall time(4026527400, 1375098, ...) -warn: ignoring syscall time(4026527312, 1, ...) -warn: ignoring syscall time(4026527048, 413, ...) -warn: ignoring syscall time(4026527048, 414, ...) -warn: ignoring syscall time(4026527288, 4026527688, ...) -warn: ignoring syscall time(4026526840, 1375098, ...) -warn: Increasing stack size by one page. -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526960, 409, ...) -warn: ignoring syscall time(4026527040, 409, ...) -warn: ignoring syscall time(4026527000, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526984, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526312, 19045, ...) -warn: ignoring syscall time(4026526832, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526840, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526848, 409, ...) -warn: ignoring syscall time(4026526936, 409, ...) -warn: ignoring syscall time(4026527008, 4026527408, ...) -warn: ignoring syscall time(4026526560, 1375098, ...) -warn: ignoring syscall time(4026527184, 18732, ...) -warn: ignoring syscall time(4026526632, 409, ...) -warn: ignoring syscall time(4026526736, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527744, 225, ...) -warn: ignoring syscall time(4026527048, 409, ...) -warn: ignoring syscall time(4026526856, 409, ...) -warn: ignoring syscall time(4026526872, 409, ...) -warn: ignoring syscall time(4026527096, 4026527496, ...) -warn: ignoring syscall time(4026526648, 1375098, ...) -warn: ignoring syscall time(4026526824, 0, ...) -warn: ignoring syscall time(4026527320, 0, ...) -warn: ignoring syscall time(4026527184, 1879089152, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall times(4026527728, 246, ...) -warn: ignoring syscall time(4026527472, 1595768, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026527472, 0, ...) -warn: ignoring syscall time(4026526912, 19045, ...) -warn: ignoring syscall time(4026526912, 17300, ...) -warn: ignoring syscall time(4026525968, 20500, ...) -warn: ignoring syscall time(4026525968, 4026526436, ...) -warn: ignoring syscall time(4026526056, 7004192, ...) -warn: ignoring syscall time(4026527512, 4, ...) -warn: ignoring syscall time(4026525760, 0, ...) -warn: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout deleted file mode 100755 index 2b1927ccc..000000000 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ /dev/null @@ -1,16 +0,0 @@ -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 5 2008 22:40:47 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 22:43:57 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 205116920000 because target called exit() -- cgit v1.2.3