From 2971b8401a4a76a774962900d9aed6e9eb4b2950 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sat, 12 Feb 2011 10:14:52 -0500 Subject: inorder:regress: host-inst-rate improved ~58% there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM) --- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tests/long/50.vortex/ref') diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index d26ecb349..5d00e7290 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27953 # Simulator instruction rate (inst/s) -host_mem_usage 1692040 # Number of bytes of host memory used -host_seconds 3160.33 # Real time elapsed on the host -host_tick_rate 13823537 # Simulator tick rate (ticks/s) +host_inst_rate 106274 # Simulator instruction rate (inst/s) +host_mem_usage 1642336 # Number of bytes of host memory used +host_seconds 831.26 # Real time elapsed on the host +host_tick_rate 52555245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.043687 # Number of seconds simulated -- cgit v1.2.3