From b4ad233c0c4aeb4f622a87ff6f7e5c4f072a2927 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Apr 2009 03:14:33 -0700 Subject: X86: Update the stats for the fix for CPUID. --- .../60.bzip2/ref/x86/linux/simple-atomic/simout | 10 +++--- .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt | 16 ++++----- .../60.bzip2/ref/x86/linux/simple-timing/simout | 10 +++--- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 40 +++++++++++----------- 4 files changed, 38 insertions(+), 38 deletions(-) (limited to 'tests/long/60.bzip2') diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 8766090d3..f3a9fb5ea 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 13:09:24 -M5 executing on maize +M5 compiled Apr 12 2009 13:26:17 +M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch +M5 started Apr 12 2009 13:27:47 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2829164056000 because target called exit() +Exiting @ tick 2829164063500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 051f5b326..47eb00d6b 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2554726 # Simulator instruction rate (inst/s) -host_mem_usage 199616 # Number of bytes of host memory used -host_seconds 1821.40 # Real time elapsed on the host -host_tick_rate 1553291459 # Simulator tick rate (ticks/s) +host_inst_rate 1691472 # Simulator instruction rate (inst/s) +host_mem_usage 197552 # Number of bytes of host memory used +host_seconds 2750.96 # Real time elapsed on the host +host_tick_rate 1028427031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653176258 # Number of instructions simulated +sim_insts 4653176270 # Number of instructions simulated sim_seconds 2.829164 # Number of seconds simulated -sim_ticks 2829164056000 # Number of ticks simulated +sim_ticks 2829164063500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5658328113 # number of cpu cycles simulated -system.cpu.num_insts 4653176258 # Number of instructions executed +system.cpu.numCycles 5658328128 # number of cpu cycles simulated +system.cpu.num_insts 4653176270 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 0d8772663..bf1d55f3d 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 13:02:28 -M5 executing on maize +M5 compiled Apr 12 2009 13:26:17 +M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch +M5 started Apr 12 2009 13:27:47 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5988064029000 because target called exit() +Exiting @ tick 5988064038000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index bca5f9f6d..32abffbae 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1632111 # Simulator instruction rate (inst/s) -host_mem_usage 207156 # Number of bytes of host memory used -host_seconds 2851.02 # Real time elapsed on the host -host_tick_rate 2100325473 # Simulator tick rate (ticks/s) +host_inst_rate 1124863 # Simulator instruction rate (inst/s) +host_mem_usage 205172 # Number of bytes of host memory used +host_seconds 4136.66 # Real time elapsed on the host +host_tick_rate 1447560054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653176258 # Number of instructions simulated +sim_insts 4653176270 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated -sim_ticks 5988064029000 # Number of ticks simulated +sim_ticks 5988064038000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.778559 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.778553 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58863922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 58863931000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 4013232881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4013232890 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4013232206 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4013232215 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5945529.194074 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.207407 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4013232881 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4013232890 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4013232206 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4013232215 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4013232881 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4013232206 # number of overall hits +system.cpu.icache.overall_hits 4013232215 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -121,7 +121,7 @@ system.cpu.icache.replacements 10 # nu system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232206 # Total number of references to valid blocks. +system.cpu.icache.total_refs 4013232215 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,13 +194,13 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25742.940427 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25742.940388 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4737814303000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 4737814312000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11976128058 # number of cpu cycles simulated -system.cpu.num_insts 4653176258 # Number of instructions executed +system.cpu.numCycles 11976128076 # number of cpu cycles simulated +system.cpu.num_insts 4653176270 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls -- cgit v1.2.3