From 57e07ac2d2daaa7469241372510395e43ebe14c0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Jan 2012 07:24:45 -0800 Subject: SE/FS: Make both SE and FS tests available all the time. --HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => 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=> tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : 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=> tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => 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tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : 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=> tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : 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=> tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : 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tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav delete mode 100644 tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 delete mode 100644 tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf delete mode 100644 tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt (limited to 'tests/long/70.twolf/ref/alpha') diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini deleted file mode 100644 index 64fd65cd8..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ /dev/null @@ -1,240 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -activity=0 -cachePorts=2 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -cpu_id=0 -dataMemPort=dcache_port -defer_registration=false -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchBuffSize=4 -fetchMemPort=icache_port -functionTrace=false -functionTraceStart=0 -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -stageTracing=false -stageWidth=4 -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout deleted file mode 100755 index ab1cbef0e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:57:18 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41833966000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt deleted file mode 100644 index db43e1bd8..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ /dev/null @@ -1,314 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.041834 # Number of seconds simulated -sim_ticks 41833966000 # Number of ticks simulated -final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111295 # Simulator instruction rate (inst/s) -host_tick_rate 50660994 # Simulator tick rate (ticks/s) -host_mem_usage 211656 # Number of bytes of host memory used -host_seconds 825.76 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -system.physmem.bytes_read 316032 # Number of bytes read from this memory -system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4938 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996214 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996224 # DTB read accesses -system.cpu.dtb.write_hits 6501905 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501928 # DTB write accesses -system.cpu.dtb.data_hits 26498119 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 9991202 # ITB hits -system.cpu.itb.fetch_misses 49 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9991251 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83667933 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. -system.cpu.activity 90.796172 # Percentage of cycles cpu is active -system.cpu.comLoads 19996198 # Number of Load instructions committed -system.cpu.comStores 6501103 # Number of Store instructions committed -system.cpu.comBranches 10240685 # Number of Branches instructions committed -system.cpu.comNops 7723346 # Number of Nop instructions committed -system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed -system.cpu.comInts 43665352 # Number of Integer instructions committed -system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26652325 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7551 # number of replacements -system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use -system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses -system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6721 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index a6f9e5430..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 9901dc40b..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:08:28 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 29167093500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 55d9dc21f..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,524 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.029167 # Number of seconds simulated -sim_ticks 29167093500 # Number of ticks simulated -final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155660 # Simulator instruction rate (inst/s) -host_tick_rate 53933893 # Simulator tick rate (ticks/s) -host_mem_usage 212576 # Number of bytes of host memory used -host_seconds 540.79 # Real time elapsed on the host -sim_insts 84179709 # Number of instructions simulated -system.physmem.bytes_read 332416 # Number of bytes read from this memory -system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5194 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25236325 # DTB read hits -system.cpu.dtb.read_misses 540509 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 25776834 # DTB read accesses -system.cpu.dtb.write_hits 7362909 # DTB write hits -system.cpu.dtb.write_misses 1032 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7363941 # DTB write accesses -system.cpu.dtb.data_hits 32599234 # DTB hits -system.cpu.dtb.data_misses 541541 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 33140775 # DTB accesses -system.cpu.itb.fetch_hits 18604047 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 18604132 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 58334188 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued -system.cpu.iq.rate 1.798857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11799539 # number of nop insts executed -system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed -system.cpu.iew.exec_branches 12916232 # Number of branches executed -system.cpu.iew.exec_stores 7364040 # Number of stores executed -system.cpu.iew.exec_rate 1.754258 # Inst execution rate -system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67789343 # num instructions producing a value -system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle -system.cpu.commit.count 91903055 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 26497301 # Number of memory references committed -system.cpu.commit.loads 19996198 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 10240685 # Number of branches committed -system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180051805 # The number of ROB reads -system.cpu.rob.rob_writes 271380444 # The number of ROB writes -system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 84179709 # Number of Instructions Simulated -system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 138495671 # number of integer regfile reads -system.cpu.int_regfile_writes 75435014 # number of integer regfile writes -system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes -system.cpu.misc_regfile_reads 715554 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8695 # number of replacements -system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use -system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses -system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use -system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7680 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3488 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5194 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5194 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119792500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59244000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179036500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11143 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.313022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.403449 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.403449 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34469.869080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34469.869080 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index c3b5c0104..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 887ca3f4e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:21 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 45951567500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index af93195e1..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,77 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951567500 # Number of ticks simulated -final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4191883 # Simulator instruction rate (inst/s) -host_tick_rate 2095941744 # Simulator tick rate (ticks/s) -host_mem_usage 202544 # Number of bytes of host memory used -host_seconds 21.92 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -system.physmem.bytes_read 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written 30920974 # Number of bytes written to this memory -system.physmem.num_reads 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes 6501103 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11030545389 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903089 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903136 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 91903136 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 2fe44f969..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 1b49765a7..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 84097b1db..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,26 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 06:10:54 -gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118740049000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index ba87aad33..000000000 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,265 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.118740 # Number of seconds simulated -sim_ticks 118740049000 # Number of ticks simulated -final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2095418 # Simulator instruction rate (inst/s) -host_tick_rate 2707308980 # Simulator tick rate (ticks/s) -host_mem_usage 211256 # Number of bytes of host memory used -host_seconds 43.86 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -system.physmem.bytes_read 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4765 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2568299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2568299 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903090 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903137 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237480098 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237480098 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 5968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- -- cgit v1.2.3