From 93c0307d418e08db609818f19f5d2b02d45e7465 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Oct 2014 23:18:29 -0500 Subject: tests: Update regressions for the new kernels and various preceeding fixes. --- .../ref/arm/linux/realview-o3-checker/config.ini | 535 ++-- .../ref/arm/linux/realview-o3-checker/simerr | 61 +- .../ref/arm/linux/realview-o3-checker/simout | 52 +- .../ref/arm/linux/realview-o3-checker/stats.txt | 2662 ++++++++++---------- 4 files changed, 1834 insertions(+), 1476 deletions(-) (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker') diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index a708031a0..c9ee24d0f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -308,6 +308,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.checker.istage2_mmu] @@ -762,6 +763,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -828,7 +830,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.cpu.l2cache.tags] type=LRU @@ -882,15 +884,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -909,8 +912,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -933,8 +936,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -990,6 +993,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -999,7 +1003,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1028,46 +1032,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1137,18 +1132,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1157,8 +1152,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1166,51 +1161,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1220,38 +1293,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1260,13 +1406,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1275,20 +1421,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1299,7 +1445,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1308,10 +1472,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1319,10 +1483,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1334,18 +1498,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1356,34 +1532,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1391,21 +1545,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1415,9 +1558,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1430,9 +1573,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1444,8 +1587,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1458,10 +1601,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1469,10 +1612,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1480,10 +1623,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1491,10 +1678,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index ec581702f..d913c3f34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -1,30 +1,49 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: LCD dual screen mode not supported -warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: 8445832500: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0 +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +warn: 81667444500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 +warn: Returning zero for read from miscreg pmcr +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0] +warn: 404836653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 +warn: instruction 'mcr bpiall' unimplemented +warn: instruction 'mcr dcisw' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 964505e0a..c5b41115c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,47 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:12:13 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990 - 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.checker.isa: ISA system set to: 0x59c2b00 0x59c2b00 + 0: system.cpu.isa: ISA system set to: 0x59c2b00 0x59c2b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525888859000 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2826845674500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 40f0cc994..2f04b9368 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542157 # Number of seconds simulated -sim_ticks 2542156879500 # Number of ticks simulated -final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826846 # Number of seconds simulated +sim_ticks 2826845674500 # Number of ticks simulated +final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45837 # Simulator instruction rate (inst/s) -host_op_rate 55223 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1932040285 # Simulator tick rate (ticks/s) -host_mem_usage 415140 # Number of bytes of host memory used -host_seconds 1315.79 # Real time elapsed on the host -sim_insts 60311972 # Number of instructions simulated -sim_ops 72661518 # Number of ops (including micro ops) simulated +host_inst_rate 73722 # Simulator instruction rate (inst/s) +host_op_rate 89421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1841455705 # Simulator tick rate (ticks/s) +host_mem_usage 559660 # Number of bytes of host memory used +host_seconds 1535.11 # Real time elapsed on the host +sim_insts 113172343 # Number of instructions simulated +sim_ops 137271263 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295608 # Number of read requests accepted -system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955787 # Per bank write bursts -system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953511 # Per bank write bursts -system.physmem.perBankRdBursts::3 951566 # Per bank write bursts -system.physmem.perBankRdBursts::4 958612 # Per bank write bursts -system.physmem.perBankRdBursts::5 955530 # Per bank write bursts -system.physmem.perBankRdBursts::6 953056 # Per bank write bursts -system.physmem.perBankRdBursts::7 951020 # Per bank write bursts -system.physmem.perBankRdBursts::8 956158 # Per bank write bursts -system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952686 # Per bank write bursts -system.physmem.perBankRdBursts::11 950200 # Per bank write bursts -system.physmem.perBankRdBursts::12 956166 # Per bank write bursts -system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953812 # Per bank write bursts -system.physmem.perBankRdBursts::15 951254 # Per bank write bursts -system.physmem.perBankWrBursts::0 6556 # Per bank write bursts -system.physmem.perBankWrBursts::1 6344 # Per bank write bursts -system.physmem.perBankWrBursts::2 6481 # Per bank write bursts -system.physmem.perBankWrBursts::3 6512 # Per bank write bursts -system.physmem.perBankWrBursts::4 6422 # Per bank write bursts -system.physmem.perBankWrBursts::5 6709 # Per bank write bursts -system.physmem.perBankWrBursts::6 6691 # Per bank write bursts -system.physmem.perBankWrBursts::7 6631 # Per bank write bursts -system.physmem.perBankWrBursts::8 6968 # Per bank write bursts -system.physmem.perBankWrBursts::9 6764 # Per bank write bursts -system.physmem.perBankWrBursts::10 6424 # Per bank write bursts -system.physmem.perBankWrBursts::11 6068 # Per bank write bursts -system.physmem.perBankWrBursts::12 7033 # Per bank write bursts -system.physmem.perBankWrBursts::13 6638 # Per bank write bursts -system.physmem.perBankWrBursts::14 6915 # Per bank write bursts -system.physmem.perBankWrBursts::15 6799 # Per bank write bursts +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory +system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 172183 # Number of read requests accepted +system.physmem.writeReqs 131246 # Number of write requests accepted +system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10992 # Per bank write bursts +system.physmem.perBankRdBursts::1 10130 # Per bank write bursts +system.physmem.perBankRdBursts::2 11200 # Per bank write bursts +system.physmem.perBankRdBursts::3 11425 # Per bank write bursts +system.physmem.perBankRdBursts::4 13122 # Per bank write bursts +system.physmem.perBankRdBursts::5 10553 # Per bank write bursts +system.physmem.perBankRdBursts::6 11175 # Per bank write bursts +system.physmem.perBankRdBursts::7 11538 # Per bank write bursts +system.physmem.perBankRdBursts::8 10354 # Per bank write bursts +system.physmem.perBankRdBursts::9 11059 # Per bank write bursts +system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::11 9259 # Per bank write bursts +system.physmem.perBankRdBursts::12 10183 # Per bank write bursts +system.physmem.perBankRdBursts::13 10761 # Per bank write bursts +system.physmem.perBankRdBursts::14 10049 # Per bank write bursts +system.physmem.perBankRdBursts::15 9748 # Per bank write bursts +system.physmem.perBankWrBursts::0 8312 # Per bank write bursts +system.physmem.perBankWrBursts::1 7765 # Per bank write bursts +system.physmem.perBankWrBursts::2 8704 # Per bank write bursts +system.physmem.perBankWrBursts::3 8608 # Per bank write bursts +system.physmem.perBankWrBursts::4 7611 # Per bank write bursts +system.physmem.perBankWrBursts::5 7956 # Per bank write bursts +system.physmem.perBankWrBursts::6 8259 # Per bank write bursts +system.physmem.perBankWrBursts::7 8579 # Per bank write bursts +system.physmem.perBankWrBursts::8 7842 # Per bank write bursts +system.physmem.perBankWrBursts::9 8532 # Per bank write bursts +system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::11 6872 # Per bank write bursts +system.physmem.perBankWrBursts::12 7611 # Per bank write bursts +system.physmem.perBankWrBursts::13 8198 # Per bank write bursts +system.physmem.perBankWrBursts::14 7543 # Per bank write bursts +system.physmem.perBankWrBursts::15 7119 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542155562500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2826845408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) -system.physmem.readPktSize::4 3351 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) +system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153413 # Read request sizes (log2) +system.physmem.readPktSize::6 168635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126865 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,331 +162,368 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads -system.physmem.totQLat 395458190750 # Total ticks spent queuing -system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads +system.physmem.totQLat 2068507750 # Total ticks spent queuing +system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 14271218 # Number of row buffer hits during reads -system.physmem.writeRowHits 90719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes -system.physmem.avgGap 157818.32 # Average gap between requests -system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states -system.physmem.memoryStateTime::REF 84888180000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing +system.physmem.readRowHits 142034 # Number of row buffer hits during reads +system.physmem.writeRowHits 95196 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes +system.physmem.avgGap 9316332.35 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states +system.physmem.memoryStateTime::REF 94394560000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states +system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.235540 # Core power per rank (mW) -system.physmem.averagePower::1 698.237375 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16348037 # Transaction distribution -system.membus.trans_dist::ReadResp 16348037 # Transaction distribution -system.membus.trans_dist::WriteReq 763357 # Transaction distribution -system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131654 # Transaction distribution -system.membus.trans_dist::ReadExResp 131654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.338580 # Core power per rank (mW) +system.physmem.averagePower::1 669.240432 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 67851 # Transaction distribution +system.membus.trans_dist::ReadResp 67850 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 90641 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution +system.membus.trans_dist::ReadExReq 135128 # Transaction distribution +system.membus.trans_dist::ReadExResp 135128 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 205 # Total snoops (count) +system.membus.snoop_fanout::samples 300256 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 216513 # Request fanout histogram -system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 300256 # Request fanout histogram +system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution -system.iobus.trans_dist::WriteReq 8176 # Transaction distribution -system.iobus.trans_dist::WriteResp 8176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.iobus.trans_dist::WriteReq 59035 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13200672 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits +system.cpu.branchPred.lookups 46931803 # Number of BP lookups +system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -507,25 +547,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 13156766 # DTB read hits -system.cpu.checker.dtb.read_misses 7319 # DTB read misses -system.cpu.checker.dtb.write_hits 11227349 # DTB write hits -system.cpu.checker.dtb.write_misses 2193 # DTB write misses -system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.read_hits 24593793 # DTB read hits +system.cpu.checker.dtb.read_misses 8242 # DTB read misses +system.cpu.checker.dtb.write_hits 19641565 # DTB write hits +system.cpu.checker.dtb.write_misses 1441 # DTB write misses +system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 4295 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses +system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 24602035 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19643006 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 24384115 # DTB hits -system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 24393627 # DTB accesses +system.cpu.checker.dtb.hits 44235358 # DTB hits +system.cpu.checker.dtb.misses 9683 # DTB misses +system.cpu.checker.dtb.accesses 44245041 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -547,28 +587,28 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits -system.cpu.checker.itb.inst_misses 4473 # ITB inst misses +system.cpu.checker.itb.inst_hits 115874779 # ITB inst hits +system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 2977 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses -system.cpu.checker.itb.hits 61486106 # DTB hits -system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61490579 # DTB accesses -system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 115879605 # ITB inst accesses +system.cpu.checker.itb.hits 115874779 # DTB hits +system.cpu.checker.itb.misses 4826 # DTB misses +system.cpu.checker.itb.accesses 115879605 # DTB accesses +system.cpu.checker.numCycles 139125744 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -594,25 +634,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31644036 # DTB read hits -system.cpu.dtb.read_misses 39518 # DTB read misses -system.cpu.dtb.write_hits 11381434 # DTB write hits -system.cpu.dtb.write_misses 10146 # DTB write misses -system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu.dtb.read_hits 25464394 # DTB read hits +system.cpu.dtb.read_misses 60419 # DTB read misses +system.cpu.dtb.write_hits 19915991 # DTB write hits +system.cpu.dtb.write_misses 9380 # DTB write misses +system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31683554 # DTB read accesses -system.cpu.dtb.write_accesses 11391580 # DTB write accesses +system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524813 # DTB read accesses +system.cpu.dtb.write_accesses 19925371 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43025470 # DTB hits -system.cpu.dtb.misses 49664 # DTB misses -system.cpu.dtb.accesses 43075134 # DTB accesses +system.cpu.dtb.hits 45380385 # DTB hits +system.cpu.dtb.misses 69799 # DTB misses +system.cpu.dtb.accesses 45450184 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -634,348 +674,349 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24158829 # ITB inst hits -system.cpu.itb.inst_misses 10513 # ITB inst misses +system.cpu.itb.inst_hits 66292387 # ITB inst hits +system.cpu.itb.inst_misses 11931 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169342 # ITB inst accesses -system.cpu.itb.hits 24158829 # DTB hits -system.cpu.itb.misses 10513 # DTB misses -system.cpu.itb.accesses 24169342 # DTB accesses -system.cpu.numCycles 499362415 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66304318 # ITB inst accesses +system.cpu.itb.hits 66292387 # DTB hits +system.cpu.itb.misses 11931 # DTB misses +system.cpu.itb.accesses 66304318 # DTB accesses +system.cpu.numCycles 260551438 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued -system.cpu.iq.rate 0.188049 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued +system.cpu.iq.rate 0.550119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176011 # number of nop insts executed -system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791373 # Number of branches executed -system.cpu.iew.exec_stores 11888962 # Number of stores executed -system.cpu.iew.exec_rate 0.186737 # Inst execution rate -system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35461894 # num instructions producing a value -system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value +system.cpu.iew.exec_nop 200946 # number of nop insts executed +system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed +system.cpu.iew.exec_branches 26532601 # Number of branches executed +system.cpu.iew.exec_stores 20878795 # Number of stores executed +system.cpu.iew.exec_rate 0.546502 # Inst execution rate +system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63282838 # num instructions producing a value +system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462353 # Number of instructions committed -system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113327248 # Number of instructions committed +system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244590 # Number of memory references committed -system.cpu.commit.loads 13512938 # Number of loads committed -system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308077 # Number of branches committed -system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. -system.cpu.commit.function_calls 991634 # Number of function calls committed. +system.cpu.commit.refs 45519928 # Number of memory references committed +system.cpu.commit.loads 24920655 # Number of loads committed +system.cpu.commit.membars 814679 # Number of memory barriers committed +system.cpu.commit.branches 26048896 # Number of branches committed +system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892513 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction -system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction +system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568215140 # The number of ROB reads -system.cpu.rob.rob_writes 154414029 # The number of ROB writes -system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311972 # Number of Instructions Simulated -system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116744 # number of integer regfile reads -system.cpu.int_regfile_writes 47012213 # number of integer regfile writes -system.cpu.fp_regfile_reads 8305 # number of floating regfile reads -system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320409321 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes -system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 26770 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.rob.rob_reads 373356629 # The number of ROB reads +system.cpu.rob.rob_writes 292965429 # The number of ROB writes +system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113172343 # Number of Instructions Simulated +system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155828809 # number of integer regfile reads +system.cpu.int_regfile_writes 88634134 # number of integer regfile writes +system.cpu.fp_regfile_reads 9591 # number of floating regfile reads +system.cpu.fp_regfile_writes 2716 # number of floating regfile writes +system.cpu.cc_regfile_reads 503010936 # number of cc regfile reads +system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes +system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65503 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -986,273 +1027,283 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 2266210 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3525536 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 36450 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959838 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1894110 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits -system.cpu.icache.overall_hits::total 23148830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses -system.cpu.icache.overall_misses::total 1005344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # 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Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 837784 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91796938 # 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miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # 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miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks +system.cpu.dcache.writebacks::total 695424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1553,32 +1609,96 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328020 # Number of tag accesses +system.iocache.tags.data_accesses 328020 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses +system.iocache.demand_misses::total 220 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 220 # number of overall misses +system.iocache.overall_misses::total 220 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- -- cgit v1.2.3