From 1297ee31f652e0ae0b2a6664b206f44ba8bcdcb0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 29 Mar 2017 18:50:49 -0700 Subject: stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power --- .../ref/arm/linux/realview-o3-dual/simerr | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr') diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 716e8ee64..41e342515 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,10 +1,15 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +info: Entering event queue @ 0. Starting simulation... warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. @@ -25,16 +30,32 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0] warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: instruction 'mcr bpiall' unimplemented +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: allocating bonus target for snoop +warn: allocating bonus target for snoop warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr @@ -45,4 +66,3 @@ warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr warn: instruction 'mcr dcisw' unimplemented -warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0] -- cgit v1.2.3